Lee Cleveland

A 2.7 V only 8 Mb/spl times/16 NOR flash memory

This paper describes a 80 ns, 2.7 V to 3.6 V single voltage supply 8 Mb/spl times/16 flash memory. It uses a high speed Vcc detector to control the wordline boost level and an intelligent programming algorithm to optimize the program time. Erase is achieved by a new low Vcc negative charge pump. The device is fabricated using a 0.5 /spl mu/m design rule, double layer metal, dual layer polysilicon, and triple well CMOS. The single transistor cell size is 1.7/spl times/1.7 /spl mu/m/sup 2/. The memory cell uses a conventional drain side channel hot electron for programming and negative gate Fowler-Nordheim tunneling on the source side for erase.

Virtual-ground sensing techniques for a 49-ns/200-MHz access time 1.8-V 256-Mb 2-bit-per-cell flash memory

Fast and accurate read operation in 1.8-V 2-bit-per-cell virtual-ground flash memories requires techniques to substantially reduce the read margin loss due to the side-leakage current and the complementary-bit disturbance. The read margin loss caused by the combination effect of these two disturbance mechanisms is serious enough to eliminate the read margin window, which is already small when the power supply voltage is about 1.8 V and when a memory cell stores 2 bits. This paper introduces for the first time the sense current recovery technique to counteract the side-leakage current effect and the differential feedback cascoded bitline control technique to minimize the complementary-bit disturbance. A 1.8-V 256-Mb 2-bit-per-cell virtual-ground flash memory employing the two techniques has been integrated using 0.13-/spl mu/m CMOS technology. These two sensing techniques are essential for the memory to achieve 49-ns initial read access and 200-MHz internal burst read access. The die size is 52 mm/sup 2/ and the cell size is 0.121 /spl mu/m/sup 2/.