Lee Seng Yeong

Wireless multimedia sensor networks onrReconfigurable hardware: information reduction techniques

Traditional wireless sensor networks (WSNs) capture scalar data such as temperature, vibration, pressure, or humidity. Motivated by the success of WSNs and also with the emergence of new technology in the form of low-cost image sensors, researchers have proposed combining image and audio sensors with WSNs to form wireless multimedia sensor networks (WMSNs). This introduces practical and research challenges, because multimedia sensors, particularly image sensors, generate huge amounts of data to be processed and distributed within the network, while sensor nodes have restricted battery power and hardware resources. This book describes how reconfigurable hardware technologies such as field-programmable gate arrays (FPGAs) offer cost-effective, flexible platforms for implementing WMSNs, with a main focus on developing efficient algorithms and architectures for information reduction, including event detection, event compression, and multicamera processing for hardware implementations. The authors include a comprehensive review of wireless multimedia sensor networks, a complete specification of a very low-complexity, low-memory FPGA WMSN node processor, and several case studies that illustrate information reduction algorithms for visual event compression, detection, and fusion. The book will be of interest to academic researchers, R&D engineers, and computer science and engineering graduate students engaged with signal and video processing, computer vision, embedded systems, and sensor networks.

Efficient processing of a rainfall simulation watershed on an FPGA-based architecture with fast access to neighbourhood pixels

This paper describes a hardware architecture to implement the watershed algorithm using rainfall simulation. The speed of the architecture is increased by utilizing a multiple memory bank approach to allow parallel access to the neighbourhood pixel values. In a single read cycle, the architecture is able to obtain all five values of the centre and four neighbours for a 4-connectivity watershed transform. The storage requirement of the multiple bank implementation is the same as a single bank implementation by using a graph-based memory bank addressing scheme. The proposed rainfall watershed architecture consists of two parts. The first part performs the arrowing operation and the second part assigns each pixel to its associated catchment basin. The paper describes the architecture datapath and control logic in detail and concludes with an implementation on a Xilinx Spartan-3 FPGA.

Uninformed pathfinding

Proposal of the boundary iterative-deepening depth-first search (BIDDFS) algorithm.The BIDDFS is extended for bidirectional searching - the bidirectional BIDDFS.A parallel approach is applied to the bidirectional BIDDFS.The BIDDFS is enhanced to search for multiple goals - the multi-goal BIDDFS.Simulations showed time improvements for the proposed uninformed algorithms. This paper presents a new pathfinding algorithm called the boundary iterative-deepening depth-first search (BIDDFS) algorithm. The BIDDFS compromises the increasing memory usage of the Dijkstras algorithm, where the memory clears enables the BIDDFS to consume less memory than the Dijkstras algorithm. The expansion redundancy of the iterative-deepening depth-first search (IDDFS) is also compensated; it is faster than the IDDFS in all of the testing instances conducted. The BIDDFS is further enhanced for bidirectional searching to allow expanding to fewer nodes and reducing pathfinding time. The bidirectional BIDDFS and the parallel bidirectional BIDDFS are also proposed. The proposed BIDDFS is further extended to the multi-goal BIDDFS, which is able to search for multiple goals present on the map in a single search. Simulation examples and comparisons have revealed the good performance of the proposed algorithms.

Efficient connected component labelling using multiple-bank memory storage

Connected component processing is a method used for segmenting an image into regions by means of grouping connected pixels of similar value. To do this, the current pixel value is compared to other connected pixel values, typically four or eight other values. Multiple read cycles would be required if these values are stored in a single bank memory. This paper presents an application of multiple-bank memory for an efficient connected components labelling. This approach has four other advantages: (1) it enables a more efficient single-pass processing of the connected components, (2) it reduces the number of clock cycles required to process each pass by enabling the architecture to process one pixel per clock cycle and when compared to the classical union-find method, (3) it reduces memory usage by eliminating the need to store temporary labels and equivalences and (4) it allows for continuous sequential labels without omitting any intermediate values.

Wireless Multimedia Sensor Network Technology

This chapter presents background material for wireless multimedia sensor network (WMSN) technology. The chapter will describe the general structure for a WMSN and various architectures and platform classifications for WMSNs. The chapter will also discuss the various components in a WMSN node such as the sensing, processing, communication, power and localisation units. The efficient processing of information in a WMSN is of primary importance, and the chapter will discuss various multi-camera network models and information reduction techniques such as event detection and event compression. The chapter concludes with a discussion of applications of WMSNs.

Image compression with short-term visual encryption using the Burrow Wheeler transform and keyed transpose

In some wireless sensor network image processing applications, visual data such as the surveillance imagery or video streaming might contain high commercial value but devalues over time. For such multimedia, the security requirement is usually low or just sufficient to disguise and protect the value of the payload for a short-term period. Multimedia compression is a necessity for these large-sized data and the unification of security and compression properties would greatly increase the practicality of the image processing algorithm. In this paper, we are presenting the image results of using the BWCA (Burrow Wheeler Compression Algorithm) on images with the proposed conditional transposition methodology (keyed transpose) for a short-term visual protection and the results for subjective metric perceptual assessment of the quality and the BWT effects on the images. (6 pages)

Closed boundary face detection in grayscale images using watershed segmentation and DSFPN

In this paper we describe a face detection method from grayscale images using a watershed based region segmentation with a neural network classifier. The algorithm segments the image into regions using a watershed algorithm. The regions are later merged and filtered leaving highly probable face region candidates. Using the Dynamic Supervised Forward Propagation Network (DSFPN), the system then verifies the possible candidate regions for faces and outputs the closed boundary for detected face regions.

Pathfinding for the navigation of visually impaired people

A navigation system using an Android mobile device for the visually impaired is explored in this paper. This paper focuses on pathfinding algorithms and their implementations on Java platform. The boundary iterative-deepening depth-first search (BIDDFS) pathfinding algorithm is extended for bidirectional searching. Fast pathfinding is applied for the BIDDFS by reducing memory read and writes cycles, proposing the optimised BIDDFS. Fast pathfinding is also extended for the bidirectional BIDDFS, proposing the fast bidirectional BIDDFS. The fast bidirectional BIDDFS uses Javas thread feature to implement a parallel structure. The optimised BIDDFS was able to record drastic improvements in pathfinding speeds compared to the standard BIDDFS. Likewise, the fast bidirectional BIDDFS recorded significant speed improvements over the parallel bidirectional BIDDFS.

FPGA Wireless Multimedia Sensor Node Hardware Platforms

This chapter presents the designs and implementations for the FPGA wireless multimedia sensor node (WMSN) hardware platforms. Two platforms will be described: a low-cost platform using the Celoxica RC10 FPGA board and a medium-cost platform using the Celoxica RC203E FPGA board. A strip-based low-memory processor based on a modified MIPS architecture will be implemented on the FPGA. For efficient processing, the strip-based MIPS processor contains customised instructions to perform the discrete wavelet transform (DWT). The chapter begins with a discussion of FPGA-based soft-core processors in wireless sensor systems and then moves on to describe the WMSN hardware platforms using the Celoxica FPGA boards. Next, the datapath and control architectures for the strip-based MIPS are discussed. The chapter concludes with an illustrative implementation of the DWT on the hardware platform using the Handel-C hardware description language. The DWT implementation will also be used in the later chapters on event detection and event compression.

Single-View Information Reduction Techniques for WMSN Using Event Detection

This chapter presents single-view information reduction techniques using the set partitioning in hierarchical tree (SPIHT) image compression algorithm. An overview of image compression models using the first and second generation compression algorithms is first described followed by the description of the SPIHT algorithm. Modifications have been introduced on the traditional SPIHT image coding technique with the aim to provide a low-memory implementation of the SPIHT coder in a wireless multimedia sensor network (WMSN) as well as improving its compression performance. The proposed approach employs a strip-based processing technique where an image is partitioned into strips and each strip is encoded separately. Besides, it also uses the new one-dimensional memory-addressing method to store the wavelet coefficients at predetermined locations in the strip buffer for ease of coding. To further reduce the memory requirements, the proposed SPIHT coding employs a new spatial orientation tree (SOT) structure and a listless approach that allow for a very low-memory implementation of the strip-based image coding. In addition, a modification to the SPIHT algorithm by reintroducing the degree-0 zerotree coding methodology was used to give a high-compression performance. Simulations show that even though the proposed image compression architecture using strip-based processing requires a much less complex hardware implementation and its efficient memory organisation uses a lesser amount of embedded memory for processing and buffering, it can still achieve a very good compression performance. The chapter concludes with the hardware implementation of the modified SPIHT coder for low-memory implementation on the strip-based MIPS processor.