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Dive into the research topics where Wai Chong Chia is active.

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Featured researches published by Wai Chong Chia.


International Journal of Sensor Networks | 2012

Low memory image stitching and compression for WMSN using strip-based processing

Wai Chong Chia; Li Wern Chew; Li-Minn Ang; Kah Phooi Seng

Due to the limited Field-Of-View (FOV) of a single camera, it is sometimes desired to extend the FOV using multiple cameras. Image stitching is one of the methods that can be used to exploit and remove the redundancy created by the overlapping FOV. However, the memory requirement and the amount of computation for conventional implementation of image stitching are very high. In this paper, this problem is resolved by performing the image stitching and compression in a strip-by-strip manner. First, the stitching parameters are determined by transmitting two reference images to an intermediate node to perform the processing. Then, these parameters are transmitted back to the visual node and stored in there. These parameters will be used to determine the way of stitching the incoming images in a strip-by-strip manner. After the stitching of a strip is done, it can be further compressed using a strip-based compression technique.


Journal of Sensors | 2013

Energy Efficiency Performance Improvements for Ant-Based Routing Algorithm in Wireless Sensor Networks

Adamu Murtala Zungeru; Kah Phooi Seng; Li-Minn Ang; Wai Chong Chia

The main problem for event gathering in wireless sensor networks (WSNs) is the restricted communication range for each node. Due to the restricted communication range and high network density, event forwarding in WSNs is very challenging and requires multihop data forwarding. Currently, the energy-efficient ant based routing (EEABR) algorithm, based on the ant colony optimization (ACO) metaheuristic, is one of the state-of-the-art energy-aware routing protocols. In this paper, we propose three improvements to the EEABR algorithm to further improve its energy efficiency. The improvements to the original EEABR are based on the following: (1) a new scheme to intelligently initialize the routing tables giving priority to neighboring nodes that simultaneously could be the destination, (2) intelligent update of routing tables in case of a node or link failure, and (3) reducing the flooding ability of ants for congestion control. The energy efficiency improvements are significant particularly for dynamic routing environments. Experimental results using the RMASE simulation environment show that the proposed method increases the energy efficiency by up to 9% and 64% in converge-cast and target-tracking scenarios, respectively, over the original EEABR without incurring a significant increase in complexity. The method is also compared and found to also outperform other swarm-based routing protocols such as sensor-driven and cost-aware ant routing (SC) and Beesensor.


Eurasip Journal on Embedded Systems | 2009

Very low-memory wavelet compression architecture using strip-based processing for implementation in wireless sensor networks

Li Wern Chew; Wai Chong Chia; Li-Minn Ang; Kah Phooi Seng

This paper presents a very low-memory wavelet compression architecture for implementation in severely constrained hardware environments such as wireless sensor networks (WSNs). The approach employs a strip-based processing technique where an image is partitioned into strips and each strip is encoded separately. To further reduce the memory requirements, the wavelet compression uses a modified set-partitioning in hierarchical trees (SPIHT) algorithm based on a degree-0 zerotree coding scheme to give high compression performance without the need for adaptive arithmetic coding which would require additional storage for multiple coding tables. A new one-dimension (1D) addressing method is proposed to store the wavelet coefficients into the strip buffer for ease of coding. A softcore microprocessor-based hardware implementation on a field programmable gate array (FPGA) is presented for verifying the strip-based wavelet compression architecture and software simulations are presented to verify the performance of the degree-0 zerotree coding scheme.


International Journal of Sensor Networks | 2012

Low-memory video compression architecture using strip-based processing for implementation in wireless multimedia sensor networks

Li Wern Chew; Wai Chong Chia; Li-Minn Ang; Kah Phooi Seng

This paper presents a very low-memory video compression architecture for implementation in a wireless multimedia sensor network. The approach employs a strip-based processing technique where a group of image sequences is partitioned into strips, and each strip is encoded separately. A new one-dimensional, memory-addressing method is proposed to store the wavelet coefficients at predetermined locations in the strip buffer for ease of coding. To further reduce the memory requirements, the video-coding scheme uses a modified set-partitioning in hierarchical trees algorithm to give a high compression performance. The proposed work is implemented using a soft-core microprocessor-based approach. Simulation tests conducted have verified that even though the proposed video compression architecture using strip-based processing requires a much less complex hardware implementation and its efficient memory organisation uses a lesser amount of embedded memory for processing and buffering, it can still achieve a very good compression performance.


international conference on intelligent human-machine systems and cybernetics | 2009

Multiview Image Compression for Wireless Multimedia Sensor Network Using Image Stitching and SPIHT Coding with EZW Tree Structure

Wai Chong Chia; Li-Minn Ang; Kah Phooi Seng

A multiview image compression framework for the Wireless Multimedia Sensor Network (WMSN) based on image stitching and SPIHT coding is proposed. This framework is designed to work with the mesh network topology that is very robust. In this framework, the images taken by neighboring sensors are stitched together with an image stitching technique to remove the overlap redundancy. The image stitching process will be carried out in certain intermediate nodes along the way towards a centralized decoder. This will help to conserve more power since the amount of data to be transmitted is reduced. In addition, the tree structure adapted by SPIHT is modified to improve the flexibility in coding the stitched image. Simulation results show that the use of image stitching with SPIHT coding can greatly remove the overlap and spatial redundancy.


Archive | 2013

Wireless multimedia sensor networks onrReconfigurable hardware: information reduction techniques

Li-Minn Ang; Kah Phooi Seng; Li Wern Chew; Lee Seng Yeong; Wai Chong Chia

Traditional wireless sensor networks (WSNs) capture scalar data such as temperature, vibration, pressure, or humidity. Motivated by the success of WSNs and also with the emergence of new technology in the form of low-cost image sensors, researchers have proposed combining image and audio sensors with WSNs to form wireless multimedia sensor networks (WMSNs). This introduces practical and research challenges, because multimedia sensors, particularly image sensors, generate huge amounts of data to be processed and distributed within the network, while sensor nodes have restricted battery power and hardware resources. This book describes how reconfigurable hardware technologies such as field-programmable gate arrays (FPGAs) offer cost-effective, flexible platforms for implementing WMSNs, with a main focus on developing efficient algorithms and architectures for information reduction, including event detection, event compression, and multicamera processing for hardware implementations. The authors include a comprehensive review of wireless multimedia sensor networks, a complete specification of a very low-complexity, low-memory FPGA WMSN node processor, and several case studies that illustrate information reduction algorithms for visual event compression, detection, and fusion. The book will be of interest to academic researchers, R&D engineers, and computer science and engineering graduate students engaged with signal and video processing, computer vision, embedded systems, and sensor networks.


Archive | 2013

Wireless Multimedia Sensor Network Technology

Li-Minn Ang; Kah Phooi Seng; Li Wern Chew; Lee Seng Yeong; Wai Chong Chia

This chapter presents background material for wireless multimedia sensor network (WMSN) technology. The chapter will describe the general structure for a WMSN and various architectures and platform classifications for WMSNs. The chapter will also discuss the various components in a WMSN node such as the sensing, processing, communication, power and localisation units. The efficient processing of information in a WMSN is of primary importance, and the chapter will discuss various multi-camera network models and information reduction techniques such as event detection and event compression. The chapter concludes with a discussion of applications of WMSNs.


international conference on computer science and information technology | 2010

Performance evaluation of feature detection in using subsampled images for image stitching

Wai Chong Chia; Li-Minn Ang; Kah Phooi Seng

Image stitching is a technique being used to stitch multiple images together to form a stitched image with higher resolution and larger field of view. It has been adopted in many research areas such as computer vision and medical applications. The first step in stitching is to first determine the overlap region or similarity. This can be done using feature extraction, follow by comparing the feature points in the images. Once the similarity is determined, the images are transformed into the same coordinate system that agreed by each other. Finally, the images can be pasted together. In this paper, the performance of various type of feature detector in extracting feature points from the subsampled version of the original images will be evaluated. The advantage of using the subsampled images is to reduce the memory requirement, and processing time.


Archive | 2009

Motion Estimation Algorithm Using One-Bit-Transform with Smoothing and Preprocessing Technique

Wai Chong Chia; Li Wern Chew; Li-Minn Ang; Kah Phooi Seng

A high performance 2D one-bit-transform (1BT) motion estimation algorithm with smoothing and preprocessing (S + P) is introduced in this paper. The 1BT technique is used to transform an 8-bit image into a 1-bit representation image (1BT image). In the 1BT motion estimation algorithm, the 8-bit current frame (c frame) and reference frame (p frame) are first transformed into their 1BT image respectively, before calculating the Sum of Absolute Difference (SAD) and performing the search operations using the Full Search Block Matching Algorithm (FSBMA). In our proposed algorithm, a smoothing threshold (ThresholdS) is incorporated into the filtering kernel, which is used to perform the transformation from 8-bit image into the 1BT image. The smoothing technique can greatly reduce the scattering noise created in the 1BT image. This will help to improve the accuracy when performing the search operations. After the transformation, the 1BT image for the c frame and p frame is divided into number of macroblocks. The macroblock in the c frame will be first compared to the macroblock at the same position in the p frame. If the SAD is below the preprocessing threshold (ThresholdP), the macroblock is considered to have negligible movement and search operation is not required. This preprocessing technique can greatly reduce the total number of search operations. Simulation results show that an improvement up to 0.65 dB, with reduction in search operation up to 95.07% is achieved. Overall, the proposed S + P technique is very suitable to be used in applications such as video conferencing and monitoring.


Archive | 2013

FPGA Wireless Multimedia Sensor Node Hardware Platforms

Li-Minn Ang; Kah Phooi Seng; Li Wern Chew; Lee Seng Yeong; Wai Chong Chia

This chapter presents the designs and implementations for the FPGA wireless multimedia sensor node (WMSN) hardware platforms. Two platforms will be described: a low-cost platform using the Celoxica RC10 FPGA board and a medium-cost platform using the Celoxica RC203E FPGA board. A strip-based low-memory processor based on a modified MIPS architecture will be implemented on the FPGA. For efficient processing, the strip-based MIPS processor contains customised instructions to perform the discrete wavelet transform (DWT). The chapter begins with a discussion of FPGA-based soft-core processors in wireless sensor systems and then moves on to describe the WMSN hardware platforms using the Celoxica FPGA boards. Next, the datapath and control architectures for the strip-based MIPS are discussed. The chapter concludes with an illustrative implementation of the DWT on the hardware platform using the Handel-C hardware description language. The DWT implementation will also be used in the later chapters on event detection and event compression.

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Li-Minn Ang

Edith Cowan University

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Kah Phooi Seng

University of Nottingham Malaysia Campus

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Li Wern Chew

University of Nottingham

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Kah Phooi Seng

University of Nottingham Malaysia Campus

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Wei Jen Chew

University of Nottingham

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