Leo G. Henry

TLP calibration, correlation, standards, and new techniques

This paper describes a constant impedance transmission line pulse system with new measurement capabilities and improved accuracy. The paper enforces a broader look at transmission line pulse (TLP) data, beyond the I-V curves. Accurate TLP measurements and actual TLP/HBM device data are used to demonstrate dV/dt effects and HBM/TLP correlation and miscorrelation. Finally, a calibration method and standard TLP test method are presented for adaptation by the industry. This is necessary to provide correlation and repeatability of experimental data.

TLP calibration, correlation, standards, and new techniques [ESD test]

This paper describes a constant impedance transmission line pulse system with new measurement capabilities and improved accuracy. The paper enforces a broader look at TLP data, beyond the I-V curves. Accurate TLP measurements and actual TLP/HBM device data are used to demonstrate dV/dt effects and HBM/TLP correlation and miscorrelation. Finally, a calibration method and standard TLP test method are presented for adaptation by the industry. This is necessary to provide correlation and repeatability of experimental data.

Developing a transient induced latch-up standard for testing integrated circuits

This paper presents the results of a search for a more effective stimulus suitable for assessing the latch-up susceptibility of integrated circuits. Different transient stimuli and amplitudes were found to have varying effectiveness in creating a latch event. The investigation also identified the inadequate response and recovery of existing test system power supplies and need for appropriate isolation techniques.

Metrology and methodology of system level ESD testing

Parameters which cause the poor reproducibility of system level ESD tests have been identified: simulator calibration methodology and insufficient simulator specifications. Results of round robin tests performed at three laboratories are reported. A better calibration methodology for ESD current measurement and additional simulator specifications for output current and radiated fields are proposed.

Investigation into socketed CDM (SDM) tester parasitics

The ESD Association standards working group 5.3.2 is analyzing the procedure and stress that is applied to a device under test (DUT) using a socketed discharge model (SDM) test system, formerly referred to as socketed CDM. Our final goal is to define an SDM tester specification that will guarantee test result reproducibility across different test equipment. This paper investigates the effect of tester background parasitics on the discharge current waveforms of an SDM tester. Characteristic waveforms were studied and SDM testing was performed on actual devices. It is shown that SDM tester parasitics determine the stress applied to the DUT. This directly affects the SDM failure threshold voltage levels and may lead to miscorrelation and nonreproducibility of test results across different SDM test systems. This paper empirically determines the relative contributions of the various tester parasitics to the total stress applied to the DUT. Our investigations indicate that the tester provides 10 to 20 pF parasitic capacitance discharge into each pin of the device. Tester background parasitic elements play such an important role in the SDM discharge event that correlation between test systems built by different manufacturers is unlikely without completely duplicating a particular tester.

Issues concerning CDM ESD verification modules-the need to move to alumina

In this work, we demonstrate that both capacitance and inductance must be the central parameters associated with the charged device model (CDM) waveform verification modules. We also propose a change from the previously used FR-4 dielectric material substrate to a more stable alumina. This improves waveform repeatability and will lead to better correlation of test results. This paper completes the groundwork for a full ESDA CDM device testing standard.

Charged device model metrology: limitations and problems

Abstract The inconsistent readings of various charged device model (CDM) test heads indicates severe metrology problems exist. Test head-to-test head response times vary by factors of two to three and no independent calibration method exists. CDM waveforms depend upon the total measurement system. This paper discusses the problems and methods necessary to the accurate capture of CDM waveforms.

The importance of standardizing CDM ESD test head parameters to obtain data correlation

Parameters associated with an observed variation in charged device model (CDM) ESD waveforms are shown to be pogo pin diameter, pogo pin length, distance between ground plane and charge plate, verification module disk diameter, dielectric area, and ground plane size. The effects on resulting discharge waveforms and solutions for improvement of existing CDM standards are discussed.

Improving CDM measurements with frequency domain specifications

Existing Charged Device Model standards have relied exclusively on time domain specifications; but devices discharge in the CDM resonant circuit at different frequencies. Accurate measurements of CDM discharge parameters require that its primary measurement components be specified in the frequency domain. Uniform frequency response measurement components are possible and described.

Issues concerning charged device model ESD verification modules − the need to move to alumina

Abstract In this work, we demonstrate that both capacitance and inductance must be the central parameters associated with the charged device model (CDM) waveform verification modules. We also propose a change from the previously used FR-4 dielectric material substrate to a more stable alumina. This improves waveform repeatability and will lead to better correlation of test results. This paper completes the groundwork for a full ESDA CDM device testing standard.