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Dive into the research topics where Robert Ashton is active.

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Featured researches published by Robert Ashton.


international reliability physics symposium | 2008

Multi-channel, high-density, ultra-low capacitance arrays for ESD and surge protection

David D. Marreiro; Sudhama C. Shastri; Mingjiao Liu; Thomas Keena; Shamsul Khan; Ali Salih; Steve Etter; Gordy Grivna; John Michael Parsey; Robert Ashton; Suem Ping Loo; Robert E. Jones; Lon Robinson; Bob Buhrman; Ryan Hurley

A novel protection device providing ultra-low line capacitance and improved ESD (J. E. Vinson et al., 2003) and surge capability is presented. Applications include stand-alone protection arrays and integrated protection in baseband- or RF-filters. A proprietary epitaxial layer and isolation capability enable high levels of surge power handling capability, while keeping line capacitance low and reducing device footprint. The response of the device to ESD and surge stresses is investigated at wafer- and package-level. Process condition variations and derived structures are studied, along with a consideration of issues related to the measurement of capacitance, ESD and surge capability.


electrical overstress electrostatic discharge symposium | 2016

HMM single site testing: Can we reproduce component failure level with the HMM document?

Mirko Scholz; Robert Ashton; Theo Smedes; Richard Derikx; Marcel Dekker; Jon Barth

The ESDA working group 5.6 has conducted single site testing to evaluate the repeatability of passfail results when using the setups in the standard practice 5.6 document. A ten times lower standard deviation is obtained in comparison to the 2011 round robin.


electrical overstress electrostatic discharge symposium | 2016

JS-002 module and product CDM result comparison to JEDEC and ESDA CDM methods

Alan Righter; Robert Ashton; B. Carn; Marty Johnson; B. Reynolds; Theo Smedes; Scott Ward; H. Wolf

CDM standard JS-002 is introduced, including the reasons for its development and the technical issues the new standard addresses. JS-002 is compared to the JEDEC JESD22-C101, ESDA and AEC Q100 CDM standards in terms of waveforms and integrated circuit pass/fail levels. JS-002 robustness levels are similar to JEDEC CDM levels.


electrical overstress/electrostatic discharge symposium | 2003

Standardization of the transmission line pulse (TLP) methodology for electrostatic discharge (ESD)

Steven H. Voldman; Robert Ashton; Jon Barth; David Bennett; Joseph C. Bernier; Michael Chaine; Jeffrey Daughton; Evan Grund; Marti Farris; Horst Gieser; Leo G. Henry; Mike Hopkins; Hugh Hyatt; M.I. Natarajan; Patrick A. Juliano; Timothy J. Maloney; Brenda McCaffrey; Larry Ting; Eugene R. Worley


electrical overstress electrostatic discharge symposium | 1999

A strategy for characterization and evaluation of ESD robustness of CMOS semiconductor technologies

Steven H. Voldman; W. Anderson; Robert Ashton; M. Chaine; Charvaka Duvvury; Timothy J. Maloney; Eugene R. Worley


electrical overstress/electrostatic discharge symposium | 2005

Voltages before and after current in HBM testers and real HBM

Jon Barth; Robert Ashton; Eugene R. Worley; John Richner


electrical overstress/electrostatic discharge symposium | 2006

Pre Pulse Voltage in the Human Body Model

Robert Ashton; Eugene R. Worley


electrical overstress electrostatic discharge symposium | 2008

Characterization of off Chip ESD protection devices

Robert Ashton; Lionel Lescouzeres


electrical overstress electrostatic discharge symposium | 2012

HMM round robin study: What to expect when testing components to the IEC 61000-4-2 waveform

Kathleen Muhonen; Robert Ashton; Theo Smedes; Mirko Scholz; Rudolf Velghe; Jon Barth; Nathaniel Peachey; Wolfgang Stadler; Evan Grund


2009 31st EOS/ESD Symposium | 2009

FCDM measurements of small devices

M. Johnson; Robert Ashton; Scott Ward

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Leo G. Henry

University of California

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Tom Meuse

Thermo Fisher Scientific

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