Leon Cloetens

Broadband access: the last mile

Driven by deregulation, a multitude of new transmission technologies have been deployed and standardized in recent years. The classical plain old telephony service (POTS) network is reused for DSL applications. Optical fiber is increasingly deployed in new networks, though its cost is still high. Air interface is used in sparsely-populated areas when deployment speed is needed. Although all these media intend to bring broadband to the home, they do it differently, using transmission principles which affect parameters such as line coding and equalization. They offer different bandwidths (less for twisted pair, highest for optical fiber) and differ in network topology (point-to-point or point-to-multi-point). Because of complex evolving standards, proposed architectures are at least partly based on programmable platforms consisting of DSPs, standard processors, and control memories. This approach is complemented by downloadable software. Design is dominated by analog aspects. Achieving transmitter performance with reasonable power consumption needs to be tackled by new structures for analog drivers, power amplifiers, ADCs, and DACs. Three families of access technology are discussed: DSL, best-known of the broadband technologies, outpacing the others in deployment speed; wireless in the local loop (WLL) and local multipoint distribution system (LMDS); and point-to-multipoint optical (PON) offering large bandwidth.

A broadband ISDN line termination chip set for 1.2 Gb/s

A broadband ISDN (integrated services digital network) line transmission chip for 1.2 Gb/s is described. Two technologies are employed: BiCMOS to handle 622-Mb/s off-board interfaces, and CMOS to handle the high-complexity functions. Throughout the system, data are transmitted at a logical rate of 622 Mb/s. In CMOS, this is realized over four parallel 155-Mb/s links, while in BiCMOS, it is realized over a single 622 Mb/s link. The CMOS chips are interconnected through homochronous links operating at 155 MHz. Each chip has about 1-M transistors operating at clock speeds of 40 to 155 MHz. Since the phase of the 155-Mb/s data is unknown, bit synchronization is required at the receiving side. A tunable delay line approach to bit synchronization was chosen. The eye diagram at the 155-Mb/s CML (common mode logic) interface is shown.<<ETX>>

Advanced architecture for a one-chip 16*16 digital switch

A one chip 16×16 digital switch is presented, designed for use in a wide variety of applications, ranging from digital mobile radio and satellite applications, to PCM switching systems (ISDN). It provides a compact, low power solution to perform in channel controlled switching of 64 kbit/s or 2 Mbit/s channels. Architecture and design examples are discussed in detail.