D. Sallaerts

A 270-kb/s 35-mW modulator IC for GSM cellular radio hand-held terminals

The modulator IC has been designed to integrate all analog baseband processing components of the European Groupe Special Mobile (GSM) digital cellular radio terminals onto a single component. The IC is located at the interface of the analog 900-MHz radio-frequency part and the baseband digital signal processing part of the mobile terminal. The modulator part time-multiplexes the receive and transmit operations and combines low-noise receive circuitry with a digital modulator. The device uses digital waveform generation and a balanced quadrature representation for both modulation and demodulation of the Gaussian minimum-shift-keying (GMSK) signal. To enhance testability of the high-density printed-circuit boards, advanced test features have also been implemented in the modulator IC. In the transmit direction, the modulator IC converts digitally encoded speech or data at an instantaneous rate of 270 kb/s to the I (in-phase) and Q (quadrature) analog signals which are used to modulate a 900-MHz carrier.<<ETX>>

A 3.3-V, low-distortion ISDN line driver with a novel quiescent current control circuit

A single chip ISDN network terminator in an advanced 3.3 V, 0.5µ CMOS technology is presented. The circuit features a U-interface line driver with a THD better than -68 dB for an output swing of 5 VppOn a 67 Ω load. A novel quiescent current control circuit is implemented which reduces the variation of the quiescent current and facilitates the drivers compensation.

A 270 kbit/s 35 mW modulator IC for GSM cellular radio hand-held terminals

The modulator IC has been designed to integrate all analog baseband processing components of the European Groupe Special Mobile (GSM) digital cellular radio terminals onto a single component. The IC is located at the interface of the analog 900-MHz radio-frequency part and the baseband digital signal processing part of the mobile terminal. The modulator part time-multiplexes the receive and transmit operations and combines low-noise receive circuitry with a digital modulator. The device uses digital waveform generation and a balanced quadrature representation for both modulation and demodulation of the Gaussian minimum-shift-keying (GMSK) signal. To enhance testability of the high-density printed-circuit boards, advanced test features have also been implemented in the modulator IC. In the transmit direction, the modulator IC converts digitally encoded speech or data at an instantaneous rate of 270 kb/s to the I (in-phase) and Q (quadrature) analog signals which are used to modulate a 900-MHz carrier. >

A broadband ISDN line termination chip set for 1.2 Gb/s

A broadband ISDN (integrated services digital network) line transmission chip for 1.2 Gb/s is described. Two technologies are employed: BiCMOS to handle 622-Mb/s off-board interfaces, and CMOS to handle the high-complexity functions. Throughout the system, data are transmitted at a logical rate of 622 Mb/s. In CMOS, this is realized over four parallel 155-Mb/s links, while in BiCMOS, it is realized over a single 622 Mb/s link. The CMOS chips are interconnected through homochronous links operating at 155 MHz. Each chip has about 1-M transistors operating at clock speeds of 40 to 155 MHz. Since the phase of the 155-Mb/s data is unknown, bit synchronization is required at the receiving side. A tunable delay line approach to bit synchronization was chosen. The eye diagram at the 155-Mb/s CML (common mode logic) interface is shown.<<ETX>>