Leonard MacEachern

Design Enhancement of Miniature Lumped-Element LTCC Bandpass Filters

We present a novel methodology for the design of miniature lumped element components embedded in a low-temperature co-fired ceramic (LTCC) package. The entire process, from initial schematic design, through individual element design, to complete device optimization is discussed. The design and fabrication of novel miniature lumped element LTCC filters is used to validate the proposed methodology. Commercial software tools are used to accurately model and simulate all aspects of the devices to ensure design success. In addition, the filters occupy only 0.03 lambda times 0.05 lambda times 0.004 lambda of a conventional low-permittivity LTCC substrate, which is among the smallest sizes reported. An advantage of these filters is that they use a true third-order topology with three multilayer L-C resonators, leading to superior stopband performance. For the first time, measured results are shown for two new bandpass filters targeted for global positioning system applications. Measured results are in good agreement with the simulations and show an insertion loss of 2.8 dB and a return loss of 21.3 dB at the center frequency of 1.64 GHz.

A Nanowatt Successive Approximation ADC with Offset Correction for Implantable Sensor Applications

An 8-bit successive approximation analog-to-digital converter (ADC) with offset correction circuitry is presented for implantable sensor applications. The ADC is designed in a 0.13mum CMOS process technology and operates with voltage supplies down to 0.35 V using MOSFETs operating in their sub-threshold region of operation. Sample rates of 60kS/s are achieved with an INL and DNL of approximately 0.26LSB and 0.35LSB respectively. The SAR ADC achieves 10.7pJ/cycle operating at 20 kS/s with a 0.4 V supply. An offset correction circuit is included to dynamically minimize the offset voltage on the comparator.

Extended robust semiconductor laser modeling for analog optical link simulations

An enhanced semiconductor laser model incorporating gain nonlinearities, gain saturation, index nonlinearities, leakage current, thermal effects, and noise effects is presented. Symbolically defined devices based on the proposed models are implemented in the Hewlett-Packard Advanced Design System computer-aided design tool. The laser model enables the simulation of the transient and steady-state dynamic characteristics of laser diodes such as carrier, photon concentration, optical power, and phase. Using the proposed model, important laser characteristics such as relaxation-oscillation peak frequency and modulation bandwidth are evaluated under different conditions and compared to published measurement results. Analog optical transmission performance limitations such as laser diode nonlinearity and noise are determined in both the time and frequency domains.

A nanowatt bandgap voltage reference for ultra-low power applications

A low voltage low power voltage reference for biomedical and embedded applications is proposed. The reference voltage has been designed in a mixed-signal 0.13 mum CMOS process for source voltages as low as 0.5 V. The reference makes use of MOSFETs in the weak inversion region to consume nanowatts of power. Monte Carlo simulations show an average temperature coefficient of 2.2ppm/degC from -40 degC to 100 degC. The circuit layout occupies approximately 25mum times 10 mum and draws 80 nA from a 500 mV supply

A miniature LTCC bandpass filter using novel resonators for GPS applications

We present a novel bandpass filter embedded in a low-temperature co-fired ceramic (LTCC) package designed for small size and robustness. Given the three-dimensional packaging capability of the LTCC substrate, the multilayer resonators are integrated into the module - eliminating the need for their discrete versions. The resonators are comprised of high Q spiral inductors that are combined with four layer parallel plate capacitors. The novel topology of placing the capacitor in the centre and two layers below the plane of the inductor allows for simultaneous area and performance optimization. The complete LTCC bandpass filter module measures only 5 mm times 5.4 mm times 0.8 mm. This version of the design utilizes discrete coupling capacitors to minimize size. The simulation results show the filter to have a centre frequency of 1.525 GHz and a bandwidth of 128 MHz. This is believed to be the smallest implementation of a LTCC bandpass filter for GPS applications.

A phase-frequency detector and a charge pump design for PLL applications

An improved phase frequency detector (PFD) and a novel charge pump (CP) for phase locked loop (PLL) applications are presented. Implemented in a CMOS 0.13 mum technology, the PFD and the CP dissipate 3.73 mW and a 460 muW DC power from a IV supply, respectively. The occupied chip area of the PFD is 68times24 mum2, and that of the CP is 68times23 mum2. With a spurious free dynamic range of a 80 dBc, a phase noise of a -95 dBc/Hz at 100 kHz offset, a low power and a small layout area the presented PFD and CP are suitable for integrated radio applications operating between 2.4 GHz and 10 GHz, such as 802.11 and WiMax for example.

Optimum Design of Wideband Compensated and Uncompensated Marchand Baluns With Step Transformers

This paper presents a design approach for wideband compensated and uncompensated Marchand baluns with stepped-impedance transformers. In order to obtain an equal-ripple bandpass response, conventional Chebyshev polynomials are modified to compensate the effect of the transfer functions dc poles. Unlike the available microwave filter design approaches, which usually require redundant elements, this approach leads to an optimum design by using the minimum number of equal length transmission line elements. Based on this design approach, both compensated and uncompensated Marchand baluns are studied. It is found that increasing difficulty arises when implementing a large bandwidth balun using the widely adopted compensated balun structure. Hence, the uncompensated balun structure becomes a better choice. To validate the proposed design approach, an uncompensated balun is designed on a standard two-sided printed circuit board. The measured results indicate that a return loss greater than 20 dB can be observed from 1 to 7.5 GHz. The phase imbalance is less than 4deg and the amplitude is less than 0.5 dB from dc to 7.2 GHz.

A nanowatt successive approximation ADC with a calibrated capacitor array for biomedical applications

An 8-bit successive approximation analog-to-digital converter (ADC) with offset correction circuitry and a tunable capacitor is presented for biomedical applications. The ADC is designed in a standard 0.13 mum CMOS process technology and operates with voltage supplies down to 0.30 V using MOSFETs operating in their sub-threshold region of operation to achieve ultra low power dissipation. Post layout simulations were used to determine that the ADC achieves 8.5 pJ/cycle energy dissipation operating at 20 kS/s with a 0.4 V supply. An offset correction circuit is included for the comparator which significantly reduces the offset voltage as a result of process and mismatch variation. The attenuation capacitor is digitally tuned and post layout simulation results show the advantage of tuning to adjust linearity and dynamic performance for the ADC.

Continuous Compensation of Binary-Weighted DAC Nonlinearities in Bandpass Delta-Sigma Modulators

We present a novel calibration technique to compensate for DAC element mismatches in bandpass multibit delta-sigma (DeltaSigma) modulators. The proposed technique is purely digital and requires only a minor modification to the modulator loop. It is compatible with binary weighted element DACs and the storage requirements for the calibrated coefficients increases only linearly with the number of quantizer bits. The calibration is performed without breaking the loop, which allows continuous tracking of environmental drifts. Simulation results show a peak signal to noise and distortion ratio (SNDR) of 68 dB after calibration for a DAC with plusmn1% mismatches, a sinusoid input signal near 1/4 of the sampling frequency and an oversampling ratio of only 10. Those results represent a 26 dB improvement over the non-calibrated case while being within 2 dB of an ideal-DAC case.

A nanowatt ADC for ultra low power applications

An 8-bit successive approximation analog-to-digital converter (ADC) for ultra low power applications is presented. It is designed in a standard 0.13mum CMOS process technology. The design can operate with low voltage supplies down to 0.45 V. It makes use of sub-threshold transistor operation to achieve nanowatts of power consumption at sample rates exceeding 60kS/s. A specially designed switch allows large input swings. Post layout simulations show an INL and DNL of approximately 0.3LSB and 0.45LSB respectively