Karim Abdelhalim

The 128-Channel Fully Differential Digital Integrated Neural Recording and Stimulation Interface

We present a fully differential 128-channel integrated neural interface. It consists of an array of 8 X 16 low-power low-noise signal-recording and generation circuits for electrical neural activity monitoring and stimulation, respectively. The recording channel has two stages of signal amplification and conditioning with and a fully differential 8-b column-parallel successive approximation (SAR) analog-to-digital converter (ADC). The total measured power consumption of each recording channel, including the SAR ADC, is 15.5 ¿W. The measured input-referred noise is 6.08 ¿ Vrms over a 5-kHz bandwidth, resulting in a noise efficiency factor of 5.6. The stimulation channel performs monophasic or biphasic voltage-mode stimulation, with a maximum stimulation current of 5 mA and a quiescent power dissipation of 51.5 ¿W. The design is implemented in 0.35-¿m complementary metal-oxide semiconductor technology with the channel pitch of 200 ¿m for a total die size of 3.4 mm × 2.5 mm and a total power consumption of 9.33 mW. The neural interface was validated in in vitro recording of a low-Mg2+/high-K+ epileptic seizure model in an intact hippocampus of a mouse.

256-Channel Neural Recording and Delta Compression Microsystem With 3D Electrodes

A 3D microsystem for multi-site penetrating extracellular neural recording from the brain is presented. A 16 times 16-channel neural recording interface integrated prototype fabricated in 0.35 mum CMOS occupies 3.5 mm times 4.5 mm area. Each recording channel dissipates 15 muW of power with input-referred noise of 7 muVrms over 5 kHz bandwidth. A switched-capacitor delta read-out data compression circuit trades recording accuracy for the output data rate. An array of 1.5 mm platinum-coated microelectrodes is bonded directly onto the die. Results of in vitro experimental recordings from intact mouse hippocampus validate the circuit design and the on-chip electrode bonding technology.

64-Channel UWB Wireless Neural Vector Analyzer SOC With a Closed-Loop Phase Synchrony-Triggered Neurostimulator

An ultra wideband (UWB) 64-channel responsive neural stimulator system-on-chip (SoC) is presented. It demonstrates the first on-chip neural vector analyzer capable of wirelessly monitoring magnitude, phase and phase synchronization of neural signals. In a closed-loop, abnormal phase synchrony triggers the programmable-waveform biphasic current-mode neural stimulator. To implement these functionalities, the SoC integrates 64 neural recording amplifiers with tunable switched-capacitor (SC) bandpass filters, 64 multiplying 8-bit SAR ADCs, 64 programmable 16-tap FIR filters, a tri-core CORDIC processor, 64 biphasic current stimulation channels, and a 3.1-10.6 GHz UWB wireless transmitter onto a 4 mm × 3 mm 0.13 μm CMOS die. To minimize both the area and power dissipation of the SoC, the SAR ADC is re-used as a multiplier for FIR filtering and as a DAC and duty cycle controller for the biphasic neural stimulator. The SoC has been validated in the early detection and abortion of seizures in freely moving rodents on-line and in early seizure detection in humans off-line.

320-Channel Active Probe for High-Resolution Neuromonitoring and Responsive Neurostimulation

We present a 320-channel active probe for high-spatial-resolution neuromonitoring and responsive neurostimulation. The probe comprises an integrated circuit (IC) cell array bonded to the back side of a pitch-matched microelectrode array. The IC enables up to 256-site neural recording and 64-site neural stimulation at the spatial resolution of 400 μm and 200 μm, respectively. It is suitable for direct integration with electrode arrays with the shank pitch of integer multiples of 200 μm. In the presented configuration, the IC is bonded with a 8 × 8 400 μm-pitch Utah electrode array (UEA) and up to additional 192 recording channels are used for peripheral neuromonitoring. The 0.35 μm CMOS circuit array has a total die size of 3.5 mm × 3.65 mm. Each stimulator channel employs a current memory for simultaneous multi-site neurostimulation, outputs 20 μA-250 μA square or arbitrary waveform current, occupies 0.02 mm 2, and dissipates 2.76 μW quiescent power. Each fully differential recording channel has two stages of amplification and filtering and an 8-bit single-slope ADC, occupies 0.035 mm 2 , and consumes 51.9 μW. The neural probe has been experimentally validated in epileptic seizure propagation studies in a mouse hippocampal slice in vitro and in responsive neurostimulation for seizure suppression in an acute epilepsy rat model in vivo .

915-MHz FSK/OOK Wireless Neural Recording SoC With 64 Mixed-Signal FIR Filters

A system-on-chip (SoC) neural recording interface with 64 channels, 64 16-tap programmable mixed-signal FIR filters and a fully integrated 915 MHz OOK/FSK PLL-based wireless transmitter is presented. Each recording channel has a fully differential amplifier with 54 dB gain and utilizes a tunable low-distortion subthreshold MOS-resistor to reject DC offsets with an input-referred noise of 6.5 μV and a CMRR of 75 dB. Each channel contains a modified 8-bit SAR ADC with an ENOB of 7.8-bits and can provide analog-digital multiplication by modifying the the sampling phase of the ADC. It is used in conjunction with 12-bit digital adders and registers to implement 64 programmable transposed FIR filters. The 915 MHz FSK/OOK transmitter offers data rates up to 1.5 Mbps and a maximum output power of 0 dBm. The 4×3 mm2 chip fabricated in a 0.13 μm CMOS process dissipates 5.03 mW from a 1.2 V supply. Experimental measurements characterize the electrical performance of the wireless SoC. In vivo measurement results from freely moving rats are also presented.

Phase-Synchronization Early Epileptic Seizure Detector VLSI Architecture

A low-power VLSI processor architecture that computes in real time the magnitude and phase-synchronization of two input neural signals is presented. The processor is a part of an envisioned closed-loop implantable microsystem for adaptive neural stimulation. The architecture uses three CORDIC processing cores that require shift-and-add operations but no multiplication. The 10-bit processor synthesized and prototyped in a standard 1.2 V 0.13 μm CMOS technology utilizes 41,000 logic gates. It dissipates 3.6 μW per input pair, and provides 1.7 kS/s per-channel throughput when clocked at 2.5 MHz. The power scales linearly with the number of input channels or the sampling rate. The efficacy of the processor in early epileptic seizure detection is validated on human intracranial EEG data.

Nanostructured CMOS Wireless Ultra-Wideband Label-Free PCR-Free DNA Analysis SoC

A fully integrated 54-channel wireless fast-scan cyclic voltammetry DNA analysis SoC is presented. The microsystem includes 546 3D nanostructured and 54 2D gold DNA sensing microelectrodes as well as 54 pH sensors. Each channel consists of a chopper-stabilized current conveyer with dynamic element matching. It is utilized as the amperometric readout circuit with a linear resolution from 8.6 pA to 350 nA. The on-chip programmable waveform generator provides a wide range of user-controlled rate and amplitude parameters with a maximum scan range of 1.2 V, and scan rate ranging between 0.1 mV/sec to 300 V/sec. A digital ultra-wideband transmitter based on a delay line architecture provides wireless data communication with data rates of up to 50 Mb/sec while consuming 400 μW. The 3 mm × 3 mm prototype fabricated in a 0.13 μm standard CMOS technology has been validated in prostate cancer synthetic DNA detection with 10 aM label-free PCR-free detection limit. Each channel occupies an area of only 0.06 mm2 and consumes 42 μW of power from a 1.2 V supply.

Low-distortion super-GOhm subthreshold-MOS resistors for CMOS neural amplifiers

A low-distortion super-GOhm subthreshold MOS resistor is designed, fabricated and experimentally validated. The circuit is utilized as a feedback element in the body of a two-stage neural recording amplifier. Linearity is experimentally validated for 0.5 Hz to 5 kHz input frequency and over 0.3 to 0.9 V output voltage dynamic range. The implemented pseudo resistor is also tunable, making the high-pass filter pole adjustable. The circuit is fabricated in 0.13-μm CMOS process and consumes 96 nW from a 1.2 V supply to realize an over 500 GΩ resistance.

256-site active neural probe and 64-channel responsive cortical stimulator

The 0.35µm CMOS active probe and stimulator enables responsive neural stimulation of the brain cortex. It monitors extracellular neural activity on 256 sites in the brain and generates 64 event-triggered current-mode neural stimuli. Each 0.035mm2 fully differential neural recording channel includes a 8-bit single slope ADC. Each 0.02mm2 neural stimulation channel reuses an OTA for both current sampling and current sourcing. The 13.5mW prototype is flip-chip bonded with a 64-shank Utah electrode array and validated in spatial recording of epileptic neural activity in the mouse hippocampus.

Inductively-powered direct-coupled 64-channel chopper-stabilized epilepsy-responsive neurostimulator with digital offset cancellation and tri-band radio

An inductively powered 0.13μm CMOS neurostimulator SoC for intractable epilepsy treatment is presented. Digital offset cancellation yields a compact 0.018mm2 DC-coupled neural recording front-end. Input chopper stabilization is performed on all 64 channels resulting in a 4.2μVrms input-referred noise. A tri-band FSK/UWB radio provides a versatile transcutaneous interface. The inductive powering system includes a 20mm × 20mm 8-layer flexible receiver coil with 40% power transfer efficiency. In-vivo chronic epilepsy treatment experimental results show an average sensitivity and specificity of seizure detection of 87% and 95%, respectively, with over 76% of all seizures aborted.