Leonard W. Schaper

Integrated passive component technology

Contributors.Preface.1 Introduction (Richard K. Ulrich).1.1 Status and Trends in Discrete Passive Components.1.2 Definitions and Configurations of Integrated Passives.1.3 Comparison to Integrated Active Devices.1.4 Substrates and Interconnect Systems for Integrated Passives.1.5 Fabrication of Integrated Passives.1.6 Reasons for Integrating Passive Devices.1.7 Problems with Integrating Passive Devices.1.8 Applications for Integrated Passives.1.9 The Past and Future of Integrated Passives.1.10 Organization of this Book.References.2 Characteristics and Performance of Planar Resistors (Richard K. Ulrich).2.1 Performance Parameters.2.2 Resistance in Electronic Materials.2.3 Sizing Integrated Resistors.2.4 Trimming.References.3 Integrated Resistor Materials and Processes (Richard K. Ulrich).3.1 Single-Component Metals.3.2 Metal Alloys and Metal-Nonmetal Compounds.3.3 Semiconductors.3.4 Cermets.3.5 Polymer Thick Film.3.6 Ink Jet Deposition.3.7 Commercialized Processes.3.8 Summary.References.4 Dielectric Materials for Integrated Capacitors (Richard K. Ulrich).4.1 Polarizability and Capacitance.4.2 Capacitance Density.4.3 Temperature Effects.4.4 Frequency and Voltage Effects.4.5 Aging Effects.4.6 Composition and Morphology Effects.4.7 Leakage and Breakdown.4.8 Dissipation Factor.4.9 Comparison to EIA Dielectric Classifications.4.10 Matching Dielectric Materials to Applications.References.5 Size and Configuration of Integrated Capacitors (Richard K. Ulrich).5.1 Comparison of Integrated and Discrete Areas.5.2 Layout Options.5.3 Tolerance.5.4 Mixed Dielectric Strategies.5.5 CV Product.5.6 Maximum Capacitance Density and Breakdown Voltage.References.6 Processing Integrated Capacitors (Richard K. Ulrich).6.1 Sputtering.6.2 CVD, PECVD and MOCVD.6.3 Anodization.6.4 Sol-Gel and Hydrothermal Ferroelectrics.6.5 Thin- and Thick-Film Polymers.6.6 Thick-Film Dielectrics.6.7 Interlayer Insulation.6.8 Interdigitated Capacitors.6.9 Capacitor Plate Materials.6.10 Trimming Integrated Capacitors.6.11 Commercialized Integrated Capacitor Technologies.6.12 Summary.References.7 Defects and Yield Issues (Richard K. Ulrich).7.1 Causes of Fatal Defects in Integrated Capacitors.7.2 Measurement of Defect Density.7.3 Defect Density and System Yield.7.3.1 Predicting Yield from Defect Density.7.4 Yield Enhancement Techniques for Capacitors.7.5 Conclusions.References.8 Electrical Performance of Integrated Capacitors (Richard K. Ulrich and Leonard W. Schaper).8.1 Modeling Ideal Passives.8.2 Modeling Real Capacitors.8.3 Electrical Performance of Discrete and Integrated Capacitors.8.4 Dissipation Factor of Real Capacitors.8.5 Measurement of Capacitor Properties.8.6 Summary.References.9 Decoupling (Leonard W. Schaper).9.1 Power Distribution.9.2 Decoupling with Discrete Capacitors.9.3 Decoupling with Integrated Capacitors.9.4 Dielectrics and Configurations for Integrated Decoupling.9.5 Integrated Decoupling as an Entry Application.References.10 Integrated Inductors (Geert J. Carchon and Walter De Raedt).10.1 Introduction.10.2 Inductor Behavior and Performance Parameters.10.3 Inductor Performance Prediction.10.4 Integrated Inductor Examples.10.5 Use of Inductors in Circuits: Examples.10.6 Conclusions.Acknowledgments.References.11 Modeling of Integrated Inductors and Resistors for Microwave Applications (Zhenwen Wang, M. Jamal Deen, and A. H. Rahal).11.1 Introduction.11.2 Modeling of Spiral Inductors.11.3 Modeling of Thin-Film Resistors.11.4 Conclusions.References.Appendix: Characteristics of Microscript Lines.12 Other Applications and Integration Technologies (Elizabeth Logan, Geert J. Carchon, Walter De Raedt, Richard K. Ulrich, and Leonard W. Schaper).12.1 Demonstration Devices Fabricated with Integrated Passives.12.2 Commercialized Thin-Film Build-Up Integrated Passives.12.3 Other Integrated Passive Technologies.12.4 Summary.Acknowledgments.References.13 The Economics of Embedded Passives (Peter A. Sandborn).13.1 Introduction.13.2 Modeling Embedded Passive Economics.13.3 Key Aspects of Modeling Embedded Passive Costs.13.4 Example Case Studies.13.5 Summary.Acknowledgments.References.14 The Future of Integrated Passives (Richard K. Ulrich).14.1 Status of Passive Integration.14.2 Issues for Implementation on Organic Substrates.14.3 Progress on Board-Level Implementation.14.4 Three Ways In for Organic Boards.14.5 Conclusion.Index.About the Editors.

Architectural implications and process development of 3-D VLSI Z-axis interconnects using through silicon vias

A through-silicon via (TSV) process provides a means of implementing complex, multichip systems entirely in silicon, with a physical packing density many times greater than todays advanced multichip modules. This technology overcomes the resistance-capacitance (RC) delays associated with long, in-plane interconnects by bringing out-of-plane logic blocks much closer electrically, and provides a connection density that makes using those blocks for random logic possible by even small system partitions. TSVs and three dimensional (3-D) stacking technology have the potential to reduce significantly the average wire length of block-to-block interconnects by stacking logic blocks vertically instead of spreading them out horizontally. Although TSVs have great potential, there are many fabrication obstacles that must be overcome. This paper discusses the architectural possibilities enabled by TSVs, and the necessary TSV dimensions for dense Z-axis interconnect among logic blocks. It then describes the TSV requirements for the Defense Advanced Research Projects Agency (DARPA)-funded Vertically Integrated Sensor Arrays (VISA) program, and how those requirements differ from a more general purpose TSV technology. Finally, the TSV fabrication process being implemented at the University of Arkansas (UA) is described in detail. Though this process is being developed for the VISA program, it embodies many of the characteristics of a widely applicable TSV technology.

Process integration for through-silicon vias

The formation of a through-silicon via (TSV) enables three-dimensional (3D) interconnects for chip-stacking applications that will be especially important for integrating heterogeneous devices. Many processing steps are involved with the major areas including: via formation; deposition of via insulation, barrier, and Cu seed films; Cu electroplating for via-fill; wafer thinning; and backside processing. The via diameter is 4–8μm, via depth is 15–20μm, and a 20μm pitch is used in this study. Each step will be described in the process flow with the considerations discussed for successful process integration.

A preliminary investigation of the effect of post-deposition polishing of diamond films on the machining behavior of diamond-coated cutting tools

Abstract The development of deposition technology and applications of diamond-coated cutting tools for machining abrasive materials has now reached a stage where viable cutting tools and machining techniques will soon be a commercial reality. Some early reports in the literature have indicated that polishing of diamond coatings may provide certain benefits in terms of reduction in cutting forces and/or improvement in surface finish of the machined component. The benefits of a polished tool are well known in the industry, as evidenced by the use of polished polycrystalline diamond and cemented carbide tools in the machining of non-ferrous materials. The present work was undertaken to investigate polishing of diamond-coated cutting tools and to study the effect of polishing on the machining behavior of such tools. In this paper we report some preliminary results obtained with polished, diamond-coated cemented carbide cutting tools in the machining of Al-Si alloys. The results suggest that polishing of diamond coating allows more efficient cutting owing to improved cutting edge geometry, leading to a reduction in cutting forces and improved chip flow during machining.

Z-axis interconnects using fine pitch, nanoscale through-silicon vias: Process development

A through-silicon via (TSV) process provides a means of implementing complex, multichip systems entirely in silicon, with a physical packing density many times greater than todays advanced MCMs. This technology overcomes the RC delays associated with long, in-plane interconnects by bringing out-of-plane logic blocks much closer electrically, and provides a connection density that makes using those blocks for random logic possible by even small system partitions. TSVs and 3-D stacking technology have the potential to significantly reduce the average wire length of block-to-block interconnects by stacking logic blocks vertically instead of spreading them out horizontally. However, even though TSVs have great potential, there are many fabrication issues that must be considered. The rationale for systems based on TSVs, and a fabrication process development plan for the creation of these structures, was presented by S. Spiesshoefer et al. (see ECTC Proc., p.631-33, 2003). The development plan included five main areas for TSV fabrication: formation of the blind vias, deposition of the insulation and seed layers, copper plating, wafer thinning, and wafer backside processing. The project goal is to create high aspect ratio vias four to six microns in diameter on 20-micron pitch in wafers that are subsequently thinned to a thickness of 15 to 20 microns. This paper will discuss the results obtained during the TSV fabrication in detail and explain the process development decisions that were made.

Embedded thin film resistors, capacitors and inductors in flexible polyimide films

The High Density Electronics Center (HiDEC) at the University of Arkansas is working with the Sheldahl MCM-L Consortium and Rensselaer Polytechnic Institute (RPI) to develop low-cost embedded resistors, capacitors, and inductors in flexible polyimide films under an ARPA contract. Embedding thin-film passive devices into polyimide layers as part of a Multichip Module (MCM) system is new. The design concept allows fabrication and testing of embedded passive devices before assembling them into an MCM-L substrate. Embedded passive devices are needed as an enhancement to present day MCM-L and MCM-D technologies. The ability to remove devices such as terminating resistors and decoupling capacitors from the surfaces of PCB boards and MCMs into a flexible film, at low cost, would be a break-through for MCM technology. The devices are made into a flexible MCM package using a 2 layer interconnect system called the Interconnected Mesh Power System (IMPS) developed and patented at the University of Arkansas. The IMPS interconnection topology incorporates fine line lithography and batch via generation to allow planar power and ground distribution, and dense signal interconnection, on only two metal layers. The materials being used are NiCr, TaN, and CrSi for the resistors and Ta/sub x/O/sub y/ and BaTiO/sub x/ for the capacitors. Contacts, interconnecting signal lines, and power lines are made with Cu metallurgy. The devices are made on a 25 /spl mu/m or 50 /spl mu/m thick polyimide film and are encapsulated with the same polyimide.

Control of sidewall slope in silicon vias using SF6∕O2 plasma etching in a conventional reactive ion etching tool

The etching of anisotropic blind vias in silicon with diameters of 5–10μm and an aspect ratio ∼2–4 with controlled sidewall inclination is reported. The motivation for this work is the creation of a vertical, or three dimensional interconnect. Via formation by reactive ion etch (RIE) processing is the focus of this project. Arrays of vias have been etched in 125 mm diam silicon (100) wafers using a photoresist mask. A parallel plate RIE system with a SF6∕O2 gas mixture is used. The effects of O2∕(SF6+O2) gas flow ratio, electrode bias, and chamber pressure on etch rate and feature profile have been studied. Visualization of the via profiles using scanning electron microscopy is used to identify the key parameters that control the sidewall slope. This slope is important for the subsequent deposition of via lining materials before filling with Cu. Our results indicate that the O2∕(SF6+O2) ratio is a key parameter in determining the sidewall slope, however the electrode bias and chamber pressure are critical...

Back side exposure of variable size through silicon vias

The formation of microscale vertical interconnects enables three-dimensional interconnects for chip stacking applications. These vertical interconnects, or metal filled through silicon vias, are formed by a series of processing steps that include silicon etch, insulation/barrier/seed deposition, electroplated Cu to fill via, wafer grinding and thinning, and back side processing for contacts. Variable diameter size vias residing in the same wafer allow flexibility in integration for many applications. Producing variable size through silicon vias (VTSVs) on a single wafer is challenging. This article presents details regarding the exposure of VTSV using a unique wafer back side processing technique. Via diameters are in the range of 10–30μm and etch depth varies with via diameter due to the commonly observed reactive ion etch lag. In this approach, the finished wafers are thicker than that produced in a previous project which reduces the risk of wafer breakage during the debonding process.

Electrical characterization of the interconnected mesh power system (IMPS) MCM topology

A significant decrease in MCM substrate production cost can be achieved by reducing the number of substrate layers from the conventional four or five (power, ground, X signal, Y signal, pad) to two or three. Besides reducing direct processing steps, yield will also increase as defect producing operations are eliminated. This paper describes the Interconnected Mesh Power System (IMPS), a new interconnection topology which leverages the production technologies of fine line lithography and batch via generation to allow planar power and ground distribution, and dense signal interconnection, on only two metal layers. Several possible implementations of the topology in MCM-D and MCM-L are described. The design of a test vehicle which characterizes both the signal transmission and power distribution properties of the IMPS topology is discussed. The test vehicle has been built in an aluminum/polyimide on silicon process developed at HiDEC. Results of signal transmission measurements (impedance, delay, and crosstalk) for various signal/power/ground configurations are presented. Power distribution characteristics (DC drops and AC noise) are presented and compared with measurements on a test vehicle implemented with solid power and ground planes. From the measured characteristics of the test vehicle, the applicability (clock frequency, power, etc.) for the IMPS topology has been determined. Most MCM applications can benefit from the substrate cost reduction enabled by IMPS. >

Integrated System Development for 3-D VLSI

A great deal of effort worldwide is being put into 3-D VLSI development. Wafer stacking is one option for manufacturing, which is good for stacking device wafers of high yield, low heat dissipation, and homogenous materials. However, for applications with moderate yield layers, high power, and differing materials, wafer stacking methods may suffer from cumulative yield issues and potential reliablility problems. The University of Arkansas is developing a novel 3-D packaging technology by die stacking. TSVs are etched and filled with copper to provide electrical connections from the front to the back side of the wafer. Copper posts and dams are plated up and used to join an individual layer to the one next to it, by forming a copper-tin intermetalic. Electrical connections are thus formed, while micro-fluid channels for cooling are created between each pair of die. Coolant is pumped through the fluid channels in order to remove heat from individual dice. Known good die can be preselected before bonding in order to address the cumulative yield problem. The die are then joined using a typical flip chip bonder. Gold to gold thermal compression can also be used, in order to bond GaAs chips with gold metalization to the silicon structure. A two layer test vehicle was designed and built to demonstrate the process. Copper posts 30 mum and 50 mum in diameter and 100 mum high have been fabricated. Tin was electroplated on daisy chain links to ensure reliable joining. The test vehicle had good daisy-chain yield of post structures and the dam provided a leak-free fluid channel. We report here the results of this work. These results allowed us to proceed with a four-layer thermal test vehicle. The TSV technology, copper dam and post technology, and assembly technology are combined in the thermal test vehicle, in which heat dissipation resistors, meandering temperature sensing resistors, and various daisy chains are included. Following sequential flip chip assembly of all four layers, the structure will be mounted with manifolds and coolant will be circulated in the system so that thermal and reliability tests can be performed. Currently this four-layer structure is being fabricated on silicon. An automated test system which will be used to determine the thermal performance and reliability has been designed and tested.