Susan L. Burkett

Architectural implications and process development of 3-D VLSI Z-axis interconnects using through silicon vias

A through-silicon via (TSV) process provides a means of implementing complex, multichip systems entirely in silicon, with a physical packing density many times greater than todays advanced multichip modules. This technology overcomes the resistance-capacitance (RC) delays associated with long, in-plane interconnects by bringing out-of-plane logic blocks much closer electrically, and provides a connection density that makes using those blocks for random logic possible by even small system partitions. TSVs and three dimensional (3-D) stacking technology have the potential to reduce significantly the average wire length of block-to-block interconnects by stacking logic blocks vertically instead of spreading them out horizontally. Although TSVs have great potential, there are many fabrication obstacles that must be overcome. This paper discusses the architectural possibilities enabled by TSVs, and the necessary TSV dimensions for dense Z-axis interconnect among logic blocks. It then describes the TSV requirements for the Defense Advanced Research Projects Agency (DARPA)-funded Vertically Integrated Sensor Arrays (VISA) program, and how those requirements differ from a more general purpose TSV technology. Finally, the TSV fabrication process being implemented at the University of Arkansas (UA) is described in detail. Though this process is being developed for the VISA program, it embodies many of the characteristics of a widely applicable TSV technology.

Process integration for through-silicon vias

The formation of a through-silicon via (TSV) enables three-dimensional (3D) interconnects for chip-stacking applications that will be especially important for integrating heterogeneous devices. Many processing steps are involved with the major areas including: via formation; deposition of via insulation, barrier, and Cu seed films; Cu electroplating for via-fill; wafer thinning; and backside processing. The via diameter is 4–8μm, via depth is 15–20μm, and a 20μm pitch is used in this study. Each step will be described in the process flow with the considerations discussed for successful process integration.

Advanced processing techniques for through-wafer interconnects

The fabrication of interconnects used in future microelectronic devices and for three-dimensional (3D) integration of these components will require advanced integrated circuit (IC) processing techniques. One attractive approach to providing increased connectivity is to use through-wafer interconnects. The primary challenge to implementing 3D stacking is the formation of these high aspect ratio interconnects with a sufficiently small diameter and, consequently, with sufficiently high density. Processing techniques to fabricate through-wafer interconnects in silicon for applications that require multichip stacking or contacts on both sides of the wafer will be described. The techniques used for fabrication of the vertical interconnects are compatible with complementary metal–oxide–semiconductor technology and executed within the thermal budget of a completed IC. The processing techniques to be described include: deep silicon etching (DRIE) to form small diameter vias, insulator lining, adhesion/barrier laye...

Polymer thickness effects on Bosch etch profiles

Time-multiplexed etching, the Bosch process, is a technique consisting of alternating etch and deposition cycles to produce high aspect-ratio etched features. The Bosch process uses SF6 and C4F8 as etch and polymer deposition gases, respectively. In these experiments, polymer thickness is controlled by both C4F8 gas flow rates and by deposition cycle time. The authors show that polymer thickness can be used to control wall angle and curvature at the base of feature walls. Wall angle is found to be independent of trench width under thin-polymer deposition conditions. Experimental results are compared to results obtained by other researchers using the more conventional simultaneous etch/deposition technique.

Temperature and field dependence of high-frequency magnetic noise in spin valve devices

The high-frequency noise of micrometer-dimension spin valve devices has been measured as a function of applied field and temperature. The data are well fit with single-domain noise models that predict that the noise power is proportional to the imaginary part of the transverse magnetic susceptibility. The fits to the susceptibility yield the ferromagnetic resonance (FMR) frequency and the magnetic damping parameter. The resonant frequency increases, from 2.1 to 3.2 GHz, as the longitudinal field varies from −2 to 4 mT and increases from 2.2 to 3.3 GHz as the temperature decreases from 400 to 100 K. The shift in the FMR frequency with temperature is larger than that expected from the temperature dependence of the saturation magnetization, indicating that other temperature-dependent anisotropy energies are present, in addition to the dominant magnetostatic energies. The measured magnetic damping parameter α decreases from 0.016 to 0.006 as the temperature decreases from 400 to 100 K. The value of the dampin...

Z-axis interconnects using fine pitch, nanoscale through-silicon vias: Process development

A through-silicon via (TSV) process provides a means of implementing complex, multichip systems entirely in silicon, with a physical packing density many times greater than todays advanced MCMs. This technology overcomes the RC delays associated with long, in-plane interconnects by bringing out-of-plane logic blocks much closer electrically, and provides a connection density that makes using those blocks for random logic possible by even small system partitions. TSVs and 3-D stacking technology have the potential to significantly reduce the average wire length of block-to-block interconnects by stacking logic blocks vertically instead of spreading them out horizontally. However, even though TSVs have great potential, there are many fabrication issues that must be considered. The rationale for systems based on TSVs, and a fabrication process development plan for the creation of these structures, was presented by S. Spiesshoefer et al. (see ECTC Proc., p.631-33, 2003). The development plan included five main areas for TSV fabrication: formation of the blind vias, deposition of the insulation and seed layers, copper plating, wafer thinning, and wafer backside processing. The project goal is to create high aspect ratio vias four to six microns in diameter on 20-micron pitch in wafers that are subsequently thinned to a thickness of 15 to 20 microns. This paper will discuss the results obtained during the TSV fabrication in detail and explain the process development decisions that were made.

Control of sidewall slope in silicon vias using SF6∕O2 plasma etching in a conventional reactive ion etching tool

The etching of anisotropic blind vias in silicon with diameters of 5–10μm and an aspect ratio ∼2–4 with controlled sidewall inclination is reported. The motivation for this work is the creation of a vertical, or three dimensional interconnect. Via formation by reactive ion etch (RIE) processing is the focus of this project. Arrays of vias have been etched in 125 mm diam silicon (100) wafers using a photoresist mask. A parallel plate RIE system with a SF6∕O2 gas mixture is used. The effects of O2∕(SF6+O2) gas flow ratio, electrode bias, and chamber pressure on etch rate and feature profile have been studied. Visualization of the via profiles using scanning electron microscopy is used to identify the key parameters that control the sidewall slope. This slope is important for the subsequent deposition of via lining materials before filling with Cu. Our results indicate that the O2∕(SF6+O2) ratio is a key parameter in determining the sidewall slope, however the electrode bias and chamber pressure are critical...

Back side exposure of variable size through silicon vias

The formation of microscale vertical interconnects enables three-dimensional interconnects for chip stacking applications. These vertical interconnects, or metal filled through silicon vias, are formed by a series of processing steps that include silicon etch, insulation/barrier/seed deposition, electroplated Cu to fill via, wafer grinding and thinning, and back side processing for contacts. Variable diameter size vias residing in the same wafer allow flexibility in integration for many applications. Producing variable size through silicon vias (VTSVs) on a single wafer is challenging. This article presents details regarding the exposure of VTSV using a unique wafer back side processing technique. Via diameters are in the range of 10–30μm and etch depth varies with via diameter due to the commonly observed reactive ion etch lag. In this approach, the finished wafers are thicker than that produced in a previous project which reduces the risk of wafer breakage during the debonding process.

Fabrication and electrical performance of through silicon via interconnects filled with a copper/carbon nanotube composite

In this work, through silicon vias (TSVs) were fabricated using a materials system consisting of a composite of copper (Cu) and vertically grown carbon nanotubes (CNTs) as a possible solution to the problems encountered when using Cu-based interconnects. A metallic seed layer, tungsten, was deposited prior to CNT growth. Tungsten replaces Cu as a seed layer due to the thermal sensitivity of Cu at CNT growth temperatures. CNTs were grown both on the wafer surface and inside the silicon vias by chemical vapor deposition. A self-directed densification process was applied to modify the shape of the CNTs from a forest with equal top and bottom dimensions into bundles with a significantly smaller dimension at the top compared to the bottom. This process maximizes the contact area between the Cu electroplating solution and the CNTs. Cu was deposited by periodic pulse electroplating after CNT growth to form the Cu/CNT composite. Wafer thinning and polishing completed the TSV fabrication forming a test configurati...

Integrated System Development for 3-D VLSI

A great deal of effort worldwide is being put into 3-D VLSI development. Wafer stacking is one option for manufacturing, which is good for stacking device wafers of high yield, low heat dissipation, and homogenous materials. However, for applications with moderate yield layers, high power, and differing materials, wafer stacking methods may suffer from cumulative yield issues and potential reliablility problems. The University of Arkansas is developing a novel 3-D packaging technology by die stacking. TSVs are etched and filled with copper to provide electrical connections from the front to the back side of the wafer. Copper posts and dams are plated up and used to join an individual layer to the one next to it, by forming a copper-tin intermetalic. Electrical connections are thus formed, while micro-fluid channels for cooling are created between each pair of die. Coolant is pumped through the fluid channels in order to remove heat from individual dice. Known good die can be preselected before bonding in order to address the cumulative yield problem. The die are then joined using a typical flip chip bonder. Gold to gold thermal compression can also be used, in order to bond GaAs chips with gold metalization to the silicon structure. A two layer test vehicle was designed and built to demonstrate the process. Copper posts 30 mum and 50 mum in diameter and 100 mum high have been fabricated. Tin was electroplated on daisy chain links to ensure reliable joining. The test vehicle had good daisy-chain yield of post structures and the dam provided a leak-free fluid channel. We report here the results of this work. These results allowed us to proceed with a four-layer thermal test vehicle. The TSV technology, copper dam and post technology, and assembly technology are combined in the thermal test vehicle, in which heat dissipation resistors, meandering temperature sensing resistors, and various daisy chains are included. Following sequential flip chip assembly of all four layers, the structure will be mounted with manifolds and coolant will be circulated in the system so that thermal and reliability tests can be performed. Currently this four-layer structure is being fabricated on silicon. An automated test system which will be used to determine the thermal performance and reliability has been designed and tested.