Leonardo Ecco

A mixed critical memory controller using bank privatization and fixed priority scheduling

Mixed critical platforms are those in which applications that have different criticalities, i.e. different levels of importance for system safety, coexist and share resources. Such platforms require a memory controller capable of providing sufficient timing independence for critical applications. Existing real-time memory controllers, however, either do not support mixed criticality or still allow a certain degree of interference between applications. The former issue leads to overly constrained, and hence more expensive, systems. The latter issue forces designers to assume the worst case latency for every individual memory transaction, which can be very conservative when applied to determine the worst-case execution time (WCET) of a task that performs many memory requests. In this paper, we address both issues. The main contributions are: (1) A memory controller that allows a predetermined number of critical and non-critical applications to coexist, while providing an interference-free memory for the former. To achieve that, we treat the memory as a set of independent virtual devices (VDs). Therefore, we also provide (2) a partitioning strategy to properly map mixed critical workloads to VDs. We present experiments that show that our controller allows DRAM sharing with no interference on critical applications and minimal performance overhead on non-critical ones (they perform on average only 15% slower in the shared environment).

Dynamic admission control for real-time networks-on-chips

Networks-on-Chip (NoCs) for real-time systems require solutions for safe and predictable sharing of network resources between transmissions with different quality-of service requirementrs. In this work, we present a mechanism for a global and dynamic admission control in NoCs designed for realtime systems. It introduces an overlay network to synchronize transmissions using arbitration units called Resource Managers (RMs), which allows a global and work-conserving scheduling. We present a formal worst-case timing analysis for the proposed mechanism and demonstrate that this solution not only exposes higher performance in simulation but, even more importantly, consistently reaches smaller formally guaranteed worst-case latencies than TDM for realistic levels of systems utilization. Our mechanism does not require modification of routers and therefore can be used together with any architecture utilizing non-blocking routers.

Improved DRAM Timing Bounds for Real-Time DRAM Controllers with Read/Write Bundling

As DRAMs become faster, the penalty to reverse the direction of their data buses increases. Yet, existing real-time memory controllers do not reorder read and write commands. Hence, timing bounds are computed by assuming an alternating pattern of reads and writes, thus accounting for several data bus direction reversals, consequently leading to suboptimal results. Therefore, in this paper, we propose a memory controller that reorders read and write commands, which minimizes reversals. Moreover, we prove through a detailed timing analysis that the effect of the reordering is bounded. Finally, we compare our approach analytically with a state-of-the-art real-time memory controller and show that our timing bounds are up to 27% better.

Workload-aware shaping of shared resource accesses in mixed-criticality systems

For mixed-criticality systems, safety standards (e.g. ISO 26262) require sufficient independence among different criticality levels, unless the entire system is certified according to the highest applicable level. We present a resource arbitration scheme that provides sufficient independence among different criticality levels w.r.t. timing properties. We exploit throughput and latency slack of critical applications by prioritizing non-critical over critical accesses and only switching priorities when necessary. By using an accurate representation of resource access patterns and workloads, the proposed arbitration scheme achieves an improved resource utilization compared to classical approaches that use simple access counters. The approach allows to provide service guarantees for critical applications, while reducing the adverse effects through strict prioritization on non-critical applications.

Minimizing DRAM Rank Switching Overhead for Improved Timing Bounds and Performance

Multi-rank DRAM modules have been identified as a flexible option for accommodating large mixed critical workloads. However, because all ranks in a module share the same multi-drop data bus, a penalty in the form of idle cycles is necessary when alternating data transfers between different ranks. Moreover, as the data bus clock frequency of DRAM modules becomes higher, such penalty increases significantly and can no longer be neglected. Therefore, in this paper, we propose a mixed critical real-time controller for multi-rank DRAM modules that minimizes rank switches. Our controller works by scheduling batches of data transfers for each rank and performing rank switches only in the end of each batch. We provide a detailed timing analysis of our approach and a comparison with a state-of-the-art counterpart. For a dual-rank scenario, our approach increases DRAM utilisation, thus reducing the latency bounds of hard real-time applications by on average 14% and decreasing the average request latency of soft real-time applications by on average 51%.

Flexible TDM-based resource management in on-chip networks

Time-division multiplexing (TDM) is the commonly used and well established solution to the problem of sharing resources in real-time Networks-on-Chip (NoCs). TDM timing is well predictable, simplifies worst-case analysis and is easy to implement. However, it introduces a constant, periodic and non-work-conserving resource sharing scheme. This challenges resource efficiency whenever the applications expose dynamics in execution time, communication volume and whenever the system is not highly loaded. In this work, we present a flexible TDM approach for NoCs where the TDM cycle adapts dynamically to the current load of data streams accessing the network. This is performed using a global arbitration layer managed by a scheduling unit called Resource Manager (RM) and a dedicated protocol. We present a formal worst-case timing analysis of this approach which allows to provide guarantees to all streams using the NoC. Finally, we demonstrate that our mechanism not only exhibits higher average performance but, even more importantly, consistently reaches smaller formally guaranteed worst-case network latencies than static TDM for realistic levels of utilization.

Real-time DRAM throughput guarantees for latency sensitive mixed QoS MPSoCs

The trend towards integration is leading to the design of multi- and many-core platforms that accommodate processing tiles (requestors) with different memory requirements. Such platforms require a memory controller capable of providing low-latency best-effort (BE) service for some requestors and guaranteed throughput (GT) for others. Although there are realtime controllers that support the concept of different traffic classes, they do not efficiently handle scenarios with multiple BE and GT requestors. We propose a memory controller that tackles this problem, providing low latency for BE requestors and real-time guarantees for GT ones. We support the guarantees with a formal timing analysis. Our experiments confirm that our approach enforces tight guarantees for GT requestors, while simultaneously reducing the latency of BE ones by up to 67%, when compared with a baseline memory controller.

Architecting high-speed command schedulers for open-row real-time SDRAM controllers

As SDRAM modules get faster and their data buses wider, researchers proposed the use of the open-row policy in command schedulers for real-time SDRAM controllers. While the real-time properties of such schedulers have been thoroughly investigated, their hardware implementation was not. Hence, in this paper, we propose a highly-parallel and multi-stage architecture that implements a state-of-the open-row real-time command scheduler. Moreover, we evaluate such architecture from the hardware overhead and performance perspectives.

Adaptive load distribution in mixed-critical Networks-on-Chip

Modern Networks-on-Chip (NoCs) must accommodate a diversity of temporal requirements e.g. provide guarantees for real-time senders with the minimum impact on performance sensitive best-effort (BE) traffic. In this work, we propose a protocol-based adaptive load distribution which by selectively detouring BE traffic i.e. load balancing, allows to significantly improve NoCs performance without costly hardware extensions. The introduced method offers, during runtime, safe and efficient integration of mixed-critical workloads through the coupling of the flow control with the path selection based on the global NoC state. The requested real-time reliability of the interconnect is achieved through predictable synchronization with control messages supported by a formal analysis and an experimental evaluation.

Ensuring safety and efficiency in networks-on-chip

Abstract Networks-on-Chip (NoCs) for real-time systems require solutions for safe and predictable sharing of network resources between transmissions with different quality of service requirements. In this work, we present a mechanism for a global and dynamic admission control in NoCs dedicated to real-time systems. It introduces an overlay network to synchronize transmissions using arbitration units called Resource Managers (RMs), which allows a global and work-conserving scheduling. We present a formal worst-case timing analysis for the proposed mechanism and demonstrate that this solution not only exposes higher performance in simulation but, even more importantly, consistently reaches smaller formally guaranteed worst-case latencies than TDM for realistic levels of systems utilization. Our mechanism does not require the modification of routers and therefore can be used together with any architecture utilizing non-blocking routers.