Adam Kostrzewa

Dynamic admission control for real-time networks-on-chips

Networks-on-Chip (NoCs) for real-time systems require solutions for safe and predictable sharing of network resources between transmissions with different quality-of service requirementrs. In this work, we present a mechanism for a global and dynamic admission control in NoCs designed for realtime systems. It introduces an overlay network to synchronize transmissions using arbitration units called Resource Managers (RMs), which allows a global and work-conserving scheduling. We present a formal worst-case timing analysis for the proposed mechanism and demonstrate that this solution not only exposes higher performance in simulation but, even more importantly, consistently reaches smaller formally guaranteed worst-case latencies than TDM for realistic levels of systems utilization. Our mechanism does not require modification of routers and therefore can be used together with any architecture utilizing non-blocking routers.

Dynamic Control for Mixed-Critical Networks-on-Chip

Networks-on-Chip (NoCs) for future real-time systems must provide service guarantees for applications with different levels of criticality. In this work, we propose an efficient mechanism for supporting mixed-criticality which combines the global, work-conserving scheduling for the end to end guarantees with the local arbitration in routers. We introduce a dynamic control layer with a central Resource Manager (RM) synchronizing transmissions with a dedicated protocol. The proposed mechanism allows to improve over existing solutions through reducing hardware overhead compared to non-blocking routers with rate control as well as temporal overhead compared to Time-Division Multiplexing (TDM). By using formal analysis, we show that RMs provide efficient service guarantees to all synchronized applications. We validate experimentally, using benchmarks, these guarantees along with the performance of the mechanism and induced overhead.

Supervised sharing of virtual channels in Networks -on-Chip

Networks-on-Chip (NoCs) for embedded multiprocessor architectures require special mechanisms for sharing resources such as links and queues in network routers. A widely used solution is virtual-channel flow control which prevents head-of-line blocking and isolates different data streams. However, the number of virtual channels (VCs) is limited by the available buffer space in the routers. Due to the evergrowing number of applications and mutual exclusive requirements it may not be possible to assign each application a unique VC. In this paper we present a Resource Broker (RB) which is an overarching mechanism that schedules NoC traffic. It allows predictable and efficient sharing of VCs without compromising isolation and Quality-of-Service guarantees. We show that by managing the NoC traffic with the RB, we drastically reduce blocking and improve the overall utilization and hence the system performance.

Minimizing DRAM Rank Switching Overhead for Improved Timing Bounds and Performance

Multi-rank DRAM modules have been identified as a flexible option for accommodating large mixed critical workloads. However, because all ranks in a module share the same multi-drop data bus, a penalty in the form of idle cycles is necessary when alternating data transfers between different ranks. Moreover, as the data bus clock frequency of DRAM modules becomes higher, such penalty increases significantly and can no longer be neglected. Therefore, in this paper, we propose a mixed critical real-time controller for multi-rank DRAM modules that minimizes rank switches. Our controller works by scheduling batches of data transfers for each rank and performing rank switches only in the end of each batch. We provide a detailed timing analysis of our approach and a comparison with a state-of-the-art counterpart. For a dual-rank scenario, our approach increases DRAM utilisation, thus reducing the latency bounds of hard real-time applications by on average 14% and decreasing the average request latency of soft real-time applications by on average 51%.

Slack-based resource arbitration for real-time Networks-on-Chip

Networks-on-Chip (NoCs) designed for real-time systems must efficiently deal with a broad diversity of traffic requirements. This requires providing latency guarantees for hard real-time transmissions with minimum impact on performance sensitive best-effort traffic. In this work, we present a novel mechanism which achieves this goal through a slack-based global and dynamic prioritization of data streams. This is performed using an overlay network and a scheduling unit combining local arbitration performed in routers with global scheduling of entire logical transmissions for end to end guarantees. Consequently, our approach allows to decrease both hardware and temporal overhead when compared with existing solutions and to achieve a performance improvement up to around 60%.

Multi-Path Scheduling for Multimedia Traffic in Safety Critical On-chip Network

Networks-on-Chip (NoCs) for contemporary multiprocessors systems must integrate complex multimedia applications which require not only high performance but also timing guarantees. However, in existing NoCs, designed for real-time systems, timing constraints are frequently implemented at the cost of decreased hardware utilization, i.e strict spatial or temporal isolation between transmissions. In this work, we propose an alternative - multi-path scheduling (MPS) - mechanism exploiting the multidimensional structure of NoCs, to combine the path selection and the temporal flow control based on the global state of the system. Consequently, MPS allows a safe sharing of NoC resources while preserving a high utilization achieved through a predictable load distribution of data traffic among different paths, reachable from source to destination. We demonstrate using benchmarks, that MPS not only provides higher average performance compared to existing solutions, but also allows to provide worst-case guarantees. We prove this important feature using formal timing analysis. Moreover, MPS induces a low implementation overhead as it can be applied to many existing wormhole-switched and performance optimized NoCs without requiring complex hardware modifications.

Flexible TDM-based resource management in on-chip networks

Time-division multiplexing (TDM) is the commonly used and well established solution to the problem of sharing resources in real-time Networks-on-Chip (NoCs). TDM timing is well predictable, simplifies worst-case analysis and is easy to implement. However, it introduces a constant, periodic and non-work-conserving resource sharing scheme. This challenges resource efficiency whenever the applications expose dynamics in execution time, communication volume and whenever the system is not highly loaded. In this work, we present a flexible TDM approach for NoCs where the TDM cycle adapts dynamically to the current load of data streams accessing the network. This is performed using a global arbitration layer managed by a scheduling unit called Resource Manager (RM) and a dedicated protocol. We present a formal worst-case timing analysis of this approach which allows to provide guarantees to all streams using the NoC. Finally, we demonstrate that our mechanism not only exhibits higher average performance but, even more importantly, consistently reaches smaller formally guaranteed worst-case network latencies than static TDM for realistic levels of utilization.

Real-time DRAM throughput guarantees for latency sensitive mixed QoS MPSoCs

The trend towards integration is leading to the design of multi- and many-core platforms that accommodate processing tiles (requestors) with different memory requirements. Such platforms require a memory controller capable of providing low-latency best-effort (BE) service for some requestors and guaranteed throughput (GT) for others. Although there are realtime controllers that support the concept of different traffic classes, they do not efficiently handle scenarios with multiple BE and GT requestors. We propose a memory controller that tackles this problem, providing low latency for BE requestors and real-time guarantees for GT ones. We support the guarantees with a formal timing analysis. Our experiments confirm that our approach enforces tight guarantees for GT requestors, while simultaneously reducing the latency of BE ones by up to 67%, when compared with a baseline memory controller.

Adaptive load distribution in mixed-critical Networks-on-Chip

Modern Networks-on-Chip (NoCs) must accommodate a diversity of temporal requirements e.g. provide guarantees for real-time senders with the minimum impact on performance sensitive best-effort (BE) traffic. In this work, we propose a protocol-based adaptive load distribution which by selectively detouring BE traffic i.e. load balancing, allows to significantly improve NoCs performance without costly hardware extensions. The introduced method offers, during runtime, safe and efficient integration of mixed-critical workloads through the coupling of the flow control with the path selection based on the global NoC state. The requested real-time reliability of the interconnect is achieved through predictable synchronization with control messages supported by a formal analysis and an experimental evaluation.

Ensuring safety and efficiency in networks-on-chip

Abstract Networks-on-Chip (NoCs) for real-time systems require solutions for safe and predictable sharing of network resources between transmissions with different quality of service requirements. In this work, we present a mechanism for a global and dynamic admission control in NoCs dedicated to real-time systems. It introduces an overlay network to synchronize transmissions using arbitration units called Resource Managers (RMs), which allows a global and work-conserving scheduling. We present a formal worst-case timing analysis for the proposed mechanism and demonstrate that this solution not only exposes higher performance in simulation but, even more importantly, consistently reaches smaller formally guaranteed worst-case latencies than TDM for realistic levels of systems utilization. Our mechanism does not require the modification of routers and therefore can be used together with any architecture utilizing non-blocking routers.