Leonardo Lanante

Low complexity compensation of frequency dependent I/Q imbalance and carrier frequency offset for direct conversion receivers

We propose a new least squares based estimation algorithm for carrier frequency offset and frequency dependent I/Q imbalance compensation with very low complexity for direct conversion receivers. Compared to conventional algorithms, our proposed estimation has considerably lesser computation due to a reduced order least squares step. Simulation results show that the proposed algorithm has about 1.5dB better accuracy in CFO estimation compared to conventional algorithms and it can completely eliminate I/Q imbalance based on BER performance results. We also showed that the proposed algorithm needs only a minimum 3rd order FIR filter to effectively remove an infinite impulse response modeled I/Q imbalance.

Hardware Implementation of High Throughput RC4 algorithm

In this paper, we present an efficient and high throughput hardware implementation of the RC4 algorithm. The main idea of the proposed architecture is the utilization of a tri-port RAM to reduce the memory resource and to increase throughput. The proposed design requires two clock cycles for generating one byte of ciphering key and uses only a block of 256 bytes RAM. These result in 50% increment of system throughput and three times reduction of RAM resource compared to the recent architectures. The proposed implementation supports variable key length from 8 to 128 bits and achieves 80 MB/s throughput at 160 MHz operating frequency. It aims to support the WEP security in the MAC layer of 600 Mbps 4×4 MIMO wireless LAN system based on IEEE 802.11n standard.

A Simple Estimation Scheme for Joint Estimation of Carrier Frequency Offset and I/Q Imbalance

This paper proposes a simple algorithm for joint estimation of carrier frequency offset and I/Q imbalance. The reduced complexity algorithm is derived from a closed form solution of the carrier frequency offset and I/Q imbalance parameters given two identical training blocks. The proposed algorithm also uses the least squares algorithm to give accurate estimate in the presence of noise. It was shown that for as little as 10 samples each from two identical OFDM symbols, the proposed algorithm can produce accurate estimate of CFO and I/Q imbalance. While the target system is OFDM, the proposed algorithm applies to any system as long as two identical data blocks are received in the receiver. Simulation results show that performance of the proposed algorithm that uses only 10 samples for complexity reduction is only 1dB below a system without CFO nor I/Q imbalance degradation. Index Terms—Carrier Frequency Offset, I/Q Imbalance, Least Squares Estimate

A New Joint Estimation Scheme for Carrier Frequency Offset and I/Q Imbalance

This paper introduces a novel algorithm for jointly estimating Carrier Frequency Offset and I/Q Imbalance for OFDM systems. The new algorithm is a closed form solution to obtain the frequency offset and I/Q Imbalance parameters in the absence of noise. In the presence of noise, the proposed algorithm uses the least squares algorithm to accurately estimate the parameters. The proposed algorithm is thus very scalable in terms of complexity. While the target system is OFDM, the proposed algorithm applies to any system as long as two identical data blocks are received in the receiver. Simulation results show that given a suitable amount of CFO, the high estimation accuracy of the proposed algorithm makes its BER performance comparable to a system without CFO and I/Q Imbalance.

Live demonstration: IEEE802.11 wireless LAN system verification platform

This is a demonstration description of our verification platform for wireless LAN applications. This verification platform consists of a motherboard containing a sizable Stratix IV FPGA, a 2.4GHz/5GHz RF daughterboard, and a highly flexible MPU daughterboard. For the MAC layer, which is implemented as a software/hardware co-design, the software part is implemented in the MPU daughterboard while the hardware part is implemented in the motherboard FPGA. For the PHY layer, which consists of a digital baseband part and analog RF part, the digital part is implemented also in the motherboard FPGA while the analog part is implemented in the RF daughterboard. We demonstrate implementation results of our platform running a IEEE802.11 based wireless LAN (WLAN) System-on-Chip (SoC) design. This demonstration is associated with Digital Signal Processing (Track 4).

Low complexity higher order QAM modulation for IDMA system

Interleave division multiple access (IDMA) is a Non-Orthogonal Multiple Access (NOMA) technique regarded as an enabling technology for next generation wireless systems. IDMA can improve the system efficiency by supporting multiple access for a large number of stations. For high spectral efficiency transmission in IDMA, previous works proposed systems in the context of Superposition Coded Modulation (SCM) where multiple layers of BPSK or QPSK modulated symbols are transmitted simultaneously. However this method has a very high complexity due to the high number of streams that need to be separated in the multi-user detection of the receiver. In this paper, instead of SCM, we employ QAM modulation up to 256-QAM for high spectral efficiency transmission. We show our receiver architecture which uses a soft demapper that significantly decreases the receiver detection complexity. While a maximum number of users that can be accommodated in the proposed system is slightly less than the conventional, our proposed system is much more suited in modern multi-mode transceivers aside from the fact that it needs about 25% complexity compared with SCM-QPSK.

A channel adaptive hybrid aggregation scheme for next generation wireless LAN

Hybrid aggregation is a frame aggregation scheme in IEEE 802.11 Medium Access Control (MAC) which combines the use of MAC Service Data Unit Aggregation (A-MSDU) and MAC Protocol Data Unit Aggregation (A-MPDU) together. Using hybrid aggregation, we can get higher throughput than using either A-MSDU or A-MPDU only scheme. However, the throughput may decrease in some high Bit Error Rate (BER) conditions depending on the length of each A-MSDU frames in the hybrid aggregated frame. An A-MSDU frame has only one Frame Check Sequence (FCS) because A-MSDU is treated as one MSDU. Therefore, even if only one MSDU in an A-MSDU frame has bit errors, whole frame retransmission is needed. This is the disadvantage of A-MSDU aggregation scheme which affects the throughput of hybrid aggregation. To reduce this A-MSDU influence on hybrid aggregation, in this paper, we propose a novel channel adaptive aggregation scheme. By controlling the number of the MSDUs for A-MSDU aggregation, we can adapt the hybrid aggregation scheme to the channel condition. Using computer simulations, we show that the proposed hybrid aggregation scheme can reduce the frame error probability and improve the throughput more efficiently than conventional one.

Low Latency IDMA With Interleaved Domain Architecture for 5G Communications

Non-orthogonal multiple access (NOMA) is a promising candidate for the future fifth generation systems because of its ability to provide greater spectral efficiency. Interleave division multiple access (IDMA) is one of the NOMA techniques that can support multiple access for a large number of users in the same bandwidth. One of the problems in the hardware implementation of IDMA is its high latency due to iterative processing. In this paper, we propose a novel architecture for the IDMA receiver with low latency while maintaining low complexity. In the conventional architecture, the IDMA receiver sequentially handles deinterleaving, despreading, spreading, and interleaving for multi-user detection. The proposed architecture which we call interleaved domain multi-user detection can perform multi-user detection directly without deinterleaving the received frame in the interference canceller iteration resulting in the decrease of latency by almost half. We also describe the memory design which is able to implement the proposed architecture. The results show that due to the reduction of the latency by half, the throughput can be increased by twice compared with the conventional architecture. VLSI implementation results show that the proposed architecture has reduced circuit area and power consumption by 53% and 58%, respectively, compared with the conventional architecture with the same throughput condition.

Design of WLAN based system for fast protocol factory automation system

This paper proposes a design of wireless communication system, particularly physical layer system (PHY) for Factory Automation (FA) system based on Wireless Local Area Network (WLAN) communication system. The designed PHY system is developed based on a fast and deterministic communication featuring a synchronous multi user round robin transmission protocol. Low overhead Packet Division Multiple Access (PDMA) scheme is utilized for Multi-user Downlink transmission, while the Frequency Division Multiple Access (FDMA) is employed for the uplink transmission. For efficient PHY implementation, several approaches on architectural aspects are also introduced. Implementation results show that the optimized design of transmitter and receiver have efficient logic resource while maintain required processing speed and error performance.

Live demonstration: Hardware-software co-verification for very large scale SoC using synopsys HAPS platform

This demo presents the verification framework for very large scale SoC System using Synopsys HAPS platform. The IEEE 802.1 lac WLAN system is selected as a case study for verification purpose. The HW/SW co-verification is carried out to confirm the feasibility of proposed system, to test data flow, and to early verify HW-SW integration. Some user experiences are also offered by proposed system such as easy controlling and fast system performance evaluation. The implementation results show that the design occupy 65,459 LUTs, 39,957 registers and 428 block RAMs, which are about 18% of available total slices in one FPGA chip. The very large SoC that utilizes up to 20 times of proposed design (equivalent to 30 Mgate) can fit into all FPGA chips inside HAPS platform.