Tran Thi Thao Nguyen

Low complexity higher order QAM modulation for IDMA system

Interleave division multiple access (IDMA) is a Non-Orthogonal Multiple Access (NOMA) technique regarded as an enabling technology for next generation wireless systems. IDMA can improve the system efficiency by supporting multiple access for a large number of stations. For high spectral efficiency transmission in IDMA, previous works proposed systems in the context of Superposition Coded Modulation (SCM) where multiple layers of BPSK or QPSK modulated symbols are transmitted simultaneously. However this method has a very high complexity due to the high number of streams that need to be separated in the multi-user detection of the receiver. In this paper, instead of SCM, we employ QAM modulation up to 256-QAM for high spectral efficiency transmission. We show our receiver architecture which uses a soft demapper that significantly decreases the receiver detection complexity. While a maximum number of users that can be accommodated in the proposed system is slightly less than the conventional, our proposed system is much more suited in modern multi-mode transceivers aside from the fact that it needs about 25% complexity compared with SCM-QPSK.

Low Latency IDMA With Interleaved Domain Architecture for 5G Communications

Non-orthogonal multiple access (NOMA) is a promising candidate for the future fifth generation systems because of its ability to provide greater spectral efficiency. Interleave division multiple access (IDMA) is one of the NOMA techniques that can support multiple access for a large number of users in the same bandwidth. One of the problems in the hardware implementation of IDMA is its high latency due to iterative processing. In this paper, we propose a novel architecture for the IDMA receiver with low latency while maintaining low complexity. In the conventional architecture, the IDMA receiver sequentially handles deinterleaving, despreading, spreading, and interleaving for multi-user detection. The proposed architecture which we call interleaved domain multi-user detection can perform multi-user detection directly without deinterleaving the received frame in the interference canceller iteration resulting in the decrease of latency by almost half. We also describe the memory design which is able to implement the proposed architecture. The results show that due to the reduction of the latency by half, the throughput can be increased by twice compared with the conventional architecture. VLSI implementation results show that the proposed architecture has reduced circuit area and power consumption by 53% and 58%, respectively, compared with the conventional architecture with the same throughput condition.

Interleaved Domain Interference Canceller for Low Latency IDMA System and Its VLSI Implementation

Interleave division multiple access (IDMA) is a potential candidate for the future fifth generation (5G) systems. In this paper, we propose a novel architecture for IDMA system with low latency while maintaining low complexity. In the conventional architecture, the IDMA receiver sequentially processes deinterleaving, despreading, spreading and interleaving for multiuser detection. The proposed architecture, which is called the interleaved domain, can perform multi-user detection directly without deinterleaving the received frame. Because of this, the interleaving is no longer needed in the interference cancellation loop resulting in the decrease of latency by half and the increase of throughput by twice. In VLSI implementation results, the proposed architecture has reduced circuit area and power consumption by 53% and 58% compared to the conventional architecture on the same throughput condition.

Low latency Interleave Division Multiple Access System

In this paper, we propose a novel architecture for IDMA system with low latency and high throughput for the uplink multi-user wireless system. The throughput of the proposed IDMA system can be improved to about double compared to the conventional IDMA system while the hardware complexity remains unchanged. To achieve this, the proposed system utilizes the interleaver/de-interleaver-less architecture to minimize the latency of the interference canceller in IDMA receiver. In the conventional architecture, the IDMA receiver sequentially processes the de-interleaving, interleaving, de-spreading and spreading that cause high latency. The proposed architecture can perform these sequential processes at the same time resulting in a reduction of interference cancellation operation cycles in half.

High-accuracy positioning system based on ToA for industrial wireless LAN

In this paper, we propose a positioning system using a time-synchronized wireless network that can achieve high positioning accuracy without being dependent on any global positioning system (GPS) devices with cm-level accuracy as the main goal and objective. The proposed system utilizes time of arrival (ToA) method to estimate the targets position. Based on the results, we can achieve time synchronization with less than 1ns accuracy with the average offset error of 0.05ns and cm-level positioning accuracy with the position error of 1.23cm through our simulation. Furthermore, increasing the number or measuring device in positioning system will increase the accuracy of positioning a target. High accuracy time synchronization is achievable by deploying proposed PTP with a high number of iteration performed inside the synchronization period. In this research, we aim to deploy the proposed system in industrial wireless LAN. It is applicable by embedding the system into customized wireless LAN chip with positioning ability.

MU-MIMO channel emulator with automatic channel sounding feedback for IEEE 802.11ac

This paper proposes a 4×4 MU-MIMO channel emulator with automatic channel sounding feedback used for beam-forming and MU-MIMO precoding features of IEEE 802.11ac. The main contribution of this paper is the design of a MU-MIMO channel emulator capable of sending channel feedback automatically to the AP from the generated channel coefficients after a programmable time duration. This function helps to evaluate the precoding algorithms without channel estimation error and uses very minimal MAC features. The second contribution is the design of single path implementation with serial processing which plays an important role on reducing the hardware complexity. The design choice makes it possible to generate channel coefficients for very high sampling rate systems with little increase in complexity. In addition, single path implementation allows the addition of the feedback channel output with only few additional nonsequential elements which would otherwise double in a parallel implementation. To demonstrate the functionality of our MU-MIMO channel emulator, we present actual hardware emulator results of precoded receive signal constellation on oscilloscope.