Leong Mook Seng

PLL based high speed functional testing

A PLL based at-speed functional testing concept, which eliminates the need for a tester-driven high-speed clock interface is presented. Jitter tolerance circuits have been implemented to provide immunity, to clock jitter. The concept was verified on a 100 mm/sup 2/ silicon device built in 0.18 /spl mu/m technology, above 200 MHz speed. Simulation results show that the concept can be extended to higher speeds.

A Miniaturized Wideband Wilkinson Power Divider

A miniaturized wideband Wilkinson Power Divider realized using OMMIC ED02AH Technology is presented. Simulation and optimization are accomplished by Advanced Design System (ADS). The final optimization results shows that it has a bandwidth of 76.5% (8.4 - 18.8 GHz), 1 dB insertion loss and good isolation (< -12 dB) between the output ports. The layout of the presented power divider is given, which shows that compacted size (0.75 × 0.45 mm2) is achieved successfully.

Compact CPW-to Microstrip transition design for MMIC packaging

In MMIC circuit design, the transitions and interconnects are essential components for integration and packaging [1-3]. However, the conventional distributed type transition circuits will result in great loss owing to their huge size, most especially in medium and low frequency band. In this paper, a new CPW-to-microstrip transition design based on lumped element circuits is proposed. The optimized design can achieve a return loss of less than 10 dB from 3 to 14 GHz and insertion loss of less than ldB from 3 to 14 GHz.

A scaling technique for partial element equivalent circuit analysis using SPICE

A scaling technique for partial element equivalent circuit (PEEC) analysis using SPICE is introduced in this letter. The perturbation series based scaling is applied to the component values extracted by the standard PEEC method to get up to an order of magnitude improvement in relative accuracy of scattering parameters with SPICE simulation. The effectiveness of the technique is verified by using the numerical example of a stripline structure and comparing the results with that of the method of moments (IE3D).

Test bench modeling and characterization for fine pitch wafer level packaged devices

This work describes an interposer hardware for testing fine pitch wafer level packaged devices. It is built to handle multi-gigahertz signal propagation using 100 micron pitch GSG probes. All the components of the test hardware socket such as the SMA connectors, coplanar transmission lines on the PCB and trampoline mesh have been modeled. A sample chip, without bumps on the pads, has also been measured. The measurement and models demonstrate that the test socket performs at 5 GHz with an insertion loss of about 3dB.

Multi resolution TLM methodology

Initially modelling using Transmission line modelling method required meshes of equal size to model the power planes. However, to model power planes with small features accurately and efficiently multi-resolution power plane modelling is required. Fine meshes will model area where small features are present and coarse meshes will model area where small features are not present. In this paper, an interfacing model is derived for multi-resolution modelling by interfacing meshes of different resolution. The derived model is verified by modelling a test power plane. Results match closely till 12 GHz and peaks and nulls pattern nicely follow upto 20 GHz when modelled by coarse meshes of dimensions 1 mm by 1 mm and finer meshes.

Approximate shielding effectiveness simulation of metallic rectangular enclosure with arbitrarily shaped apertures

An approximate simulation method has been developed for the shielding effectiveness of a rectangular enclosure with arbitrarily shaped apertures. Mutual coupling between. these apertures is considered. Theoretical computation of the shielding effectiveness is in good agreement with measurements.