Jayasanker Jayabalan

Multi-Gigahertz Testing of Wafer-Level Packaged Devices

The authors are developing alternative approaches for wafer-level packaging (WLP) of high-performance, high I/O-density chips. The electrical contacts are patterned onto the wafer surface using lithographic processes in order to provide high density I/Os at a very low cost per pin. In order to fully exploit these new packaging technologies, a compatible testing approach is also needed. This paper describes one of the WLP I/O structures, a new bare-die test socket, and a low-cost multi-GHz miniature tester. Our initial objective for this WLP technology is 5 Gbps; and the operation of interconnects, the bare-die test socket, and the miniature tester at this rate and slightly higher (6.4 Gbps), was demonstrated. The miniature tester alone is demonstrated up to 8 Gbps

A scaling technique for partial element equivalent circuit analysis using SPICE

A scaling technique for partial element equivalent circuit (PEEC) analysis using SPICE is introduced in this letter. The perturbation series based scaling is applied to the component values extracted by the standard PEEC method to get up to an order of magnitude improvement in relative accuracy of scattering parameters with SPICE simulation. The effectiveness of the technique is verified by using the numerical example of a stripline structure and comparing the results with that of the method of moments (IE3D).

Test strategies for fine pitch wafer level packaged devices

The objective of this work is to be able to test wafer level packaged devices at 5 GHz given tight mechanical constraints such as very fine pitch (of the order of 100 micron) and large pin count of thousands. Good electrical contact at the wafer level after the attachment of interconnects is needed for producing reliable electrical test results.. This paper describes the details of modeling, fabrication and the test methodology as applied to the electrical characterization of fine pitch and large pin count wafer level packaged devices.

Test bench modeling and characterization for fine pitch wafer level packaged devices

This work describes an interposer hardware for testing fine pitch wafer level packaged devices. It is built to handle multi-gigahertz signal propagation using 100 micron pitch GSG probes. All the components of the test hardware socket such as the SMA connectors, coplanar transmission lines on the PCB and trampoline mesh have been modeled. A sample chip, without bumps on the pads, has also been measured. The measurement and models demonstrate that the test socket performs at 5 GHz with an insertion loss of about 3dB.

Novel circuit model for three-dimensional geometries with multilayer dielectrics

The partial-element equivalent-circuit (PEEC) method is generalized to include multilayer dielectric interfaces. The boundary between two different dielectrics is treated as a new region to develop an interface Greens function. The interface Greens function is subsequently used to calculate the capacitances and inductances of interface surface cells. The method is first verified, using a microstrip to evaluate the quasi-static capacitance, with the method of Wheeler. It is then extended to the PEEC formulation and applied to coupled microstrip-line filter with multilayered dielectrics. The results are compared with that of the method of moments. Agreement is found in the prediction of resonant frequencies and S-parameters.

PEEC model for multiconductor systems including dielectric mesh

In this paper, an elastomer dielectric mesh with and without metallization is modeled by the partial element equivalent circuit (PEEC) method. The model is verified through frequency domain measurements on a coplanar transmission structure sample. Due to good electrical contactability and mechanical compliance, this material has novel applications for fine pitch wafer level device testing at multi-gigahertz frequencies.

Signal Delay Based Temperature Determination for Production Testing of Advanced Packages

This paper describes a technique to determine electrical test temperature of devices made of conventional packages like QFP and BGA as well as new packaging technologies such as system-in-package (SIP) and wafer level packages. It is based on the signal propagation delays that are sensitive to temperatures within the chip. The technique was applied to a QFP device, fabricated in 0.35 micron technology, that operates at 25 MHz with an average power consumption of about 0.5 Watt. The package geometry and the test environment have been numerically modeled. The signal delay measurement results are found to agree with the estimates based on numerical modeling. This technique will be useful in direct evaluation of production test temperatures when the package geometry and test environment are harder to model.

A Novel Test Strategy for Fine Pitch Wafer-Level Packaged Devices

This paper describes an innovative test strategy comprising a compliant elastomer mesh for testing fine pitch wafer-level package (WLP) devices. The test probe, hardware, and sample preparation processes are detailed. The components of the test hardware socket such as the SMA connectors, coplanar transmission lines on the PCB, via, off-chip interconnect, and elastomer mesh probe have been modeled. A complete system-level model, with off-chip interconnects on the WLP device pads, has been developed. The measurement and model demonstrate that the prototype test socket performs at 5 GHz with an insertion loss of about 3 dB. WLP device with Bed-of-Nail interconnects are characterized. Functional test features of the system are also addressed.

ENERGETICS OF COPPER NANOWIRES

The present work calculates the size dependent behaviour of Fermi energy, work function, and the ionization potential of finite copper nanowire by using a free electron model. A uniform conductor of finite length and a square cross section is assumed to model the copper nanowires. The energy spectrum of the wire is determined by solving the one-electron Schrodinger equation with the potential described by a square well potential. The details of size dependence of electronic characteristics of the copper nanowires are illustrated in this present work.