Leonid Fursin

4H-SiC normally-off vertical junction field-effect transistor with high current density

4H-silicon carbide (SiC) normally-off vertical junction field-effect transistor (JFET) is developed in a purely vertical configuration without internal lateral JFET gates. The 2.1-/spl mu/m vertical p/sup +/n junction gates are created on the side walls of deep trenches by tilted aluminum (Al) implantation. Normally-off operation with blocking voltage V/sub bl/ of 1 726 V is demonstrated with an on-state current density of 300 A/cm/sup 2/ at a drain voltage of 3 V. The low specific on-resistance R/sub on-sp/ of 3.6 m/spl Omega/cm/sup 2/ gives the V/sub bl//sup 2//R/sub on-sp/ value of 830 MW/cm/sup 2/, surpassing the past records of both unipolar and bipolar 4H-SiC power switches.

Fabrication and Characterization of High-Current-Gain 4H-SiC Bipolar Junction Transistors

This paper reports on newly developed high-performance 4H-SiC bipolar junction transistors (BJT) with improved current gain and power handling capabilities based on an intentionally designed continuously grown 4H-SiC BJT wafer. The measured dc common-emitter current gain is as high as 70, the specific ON-state resistance (RSP-ON) is as low as 3.0 mOmegamiddotcm2, and the open-base breakdown voltage (VCEO) reaches 1750 V. Large-area 4H-SiC BJTs with a footprint of 4.1 times 4.1 mm have been successfully packaged into a high-gain (beta = 50.8) high-power (80 A times 700 V) all-SiC copack and evaluated at high temperature up to 250degC. Small 4H-SiC BJTs have been stress tested under a continuous collector current density of 100 A/cm2 for 24 h and, for the first time, have shown no obvious forward voltage drift and no current gain degradation. Numerical simulations and experimental results have confirmed that simultaneous high current gain and high open-base breakdown voltage could be achieved in 4H-SiC BJTs.

A high current gain 4H-SiC NPN power bipolar junction transistor

This work reports the development of high power 4H-SiC bipolar junction transistors (BJTs) by using reduced implantation dose for p+ base contact region and annealing in nitric oxide of base-to-emitter junction passivation oxide for 2 hours at 1150/spl deg/C. The transistor blocks larger than 480 V and conducts 2.1 A (J/sub c/=239 A/cm/sup 2/) at V/sub ce/=3.4 V, corresponding to a specific on-resistance (R/sub sp on/) of 14 m/spl Omega/cm/sup 2/, based on a drift layer design of 12 /spl mu/m doped to 6/spl times/10/sup 15/cm/sup -3/. Current gain /spl beta//spl ges/35 has been achieved for collector current densities ranging from J/sub c/=40 A/cm/sup 2/ to 239 A/cm/sup 2/ (I/sub c/=2.1 A) with a peak current gain of 38 at J/sub c/=114 A/cm/sup 2/.

Rheology and Thermal Conductivity of Diamond Powder-Filled Liquid Epoxy Encapsulants for Electronic Packaging

The traditional silica-based epoxy system used for electronic packaging has a poor thermal conductivity of less than 1 W/mK and no longer meets the increasingly stringent thermal management requirements of many packaging applications. The current commercial availability of low-cost diamond powders with very high-thermal conductivity makes it possible to consider diamond powder-filled epoxy for high-end product packaging. This paper reports the design, rheology, and experimentally determined thermal conductivity results on the multimodal diamond powder-filled epoxy system for liquid encapsulants. Rheology studies of the monomodal diamond powder in epoxy show the necessity of the use of surfactants when the powder sizes are below 10 mum. A high-thermal conductivity of 4.1 W/mK was achieved for epoxy-filled by 68% volume loading of diamond powders, which required a multimodal particle size distribution (nine sizes). Comparative measurements of electronic junction temperatures of Si diodes sealed by the diamond powder-filled epoxy and commercial silica-epoxy show a much better thermal performance of the diamond-filled epoxy, which suggests the potential application of the diamond-filled epoxy for packaging high-end electronic products.

On the temperature coefficient of 4H-SiC BJT current gain

Abstract In this paper, the temperature coefficient of 4H-SiC NPN BJT current gain is studied by way of numerical simulations. In general, 4H-SiC NPN BJT would have a positive temperature coefficient (PTC) for the common emitter current gain if the acceptor ionization energy is smaller than 170 meV. Both PTC and negative temperature coefficient (NTC) can occur in 4H-SiC NPN BJT with an aluminum-doped base. High base doping concentration is required to obtain a wide range of current density with a NTC for current gain, especially when the electron lifetime in base is low. For a base doping concentration of 2.5×10 17 cm −3 , the NTC for current gain is obtained for current density up to 300 A/cm 2 , even when the electron lifetime is as low as 48 ns. The experimental results are also reported.

1000-V 9.1-

A 4H-SiC normally off vertical channel lateral reduced-surface electric-field (RESURF) junction field-effect transistor (JFET) with a blocking voltage Vbr of 1028 V and a specific on-resistance R on-sp of 9.1 mOmegamiddotcm2 has been experimentally demonstrated. The device has a Vbr 2/Ron-sp figure-of-merit of 116 MW/cm2, which is the highest value achieved to date on a 4H-SiC lateral power transistor. Also reported is a larger JFET that is capable of handling over 0.5-A current on an active area of 4.01times10-3 cm2. The fabricated double-RESURF devices have a vertical channel length of 1.8 mum, created by tilted aluminum (Al) implantation on the sidewalls of deep trenches, and a lateral drift-region length of 7.5 mum. In addition, low-voltage logic-inverter circuits based on the same lateral JFET process have been monolithically integrated on the same chip. Proper logic-inverter function has also been demonstrated

\hbox{m}\Omega \cdot \hbox{cm}^{2}

This letter reports the demonstration of a 4H-SiC trenched and implanted vertical-junction field-effect transistor (TI-VJFET). The p/sup +/n junction gates are created on the sidewalls of deep trenches by angled Al implantation, which eliminates the need for epitaxial regrowth during the JFET fabrication. Blocking voltages up to 1710 V has been achieved with a voltage supporting drift layer of only 9.5 /spl mu/m by using a two-step junction termination extension. The TI-VJFET shows a low specific on-resistance R/sub ON-sp/ of 2.77m/spl Omega/cm/sup 2/, corresponding to a record high value of V/sub B//R/sub ON-sp/ equal to 1056 MW/cm/sup 2/.

Normally Off 4H-SiC Lateral RESURF JFET for Power Integrated Circuit Applications

A novel lateral junction field-effect transistor (JFET)-based power IC technology in 4H-SiC is presented in detail covering device and circuit design, fabrication, and characterization. The optimal reduced surface field design for the lateral power JFET has been carried out and implemented in the IC fabrication. Since this technology has great promise at high temperatures, the temperature dependences (from room temperature to 300degC) of the threshold voltage, transconductance, resistance, and electron mobility have been fully characterized. Advantages of the SiC vertical-channel lateral JFET (VC-LJFET) technology, such as lower output capacitance (Coss) for lateral power JFETs and adjustable threshold voltages at mask design level, are also discussed. Finally, a monolithic power IC chip integrating a power lateral JFET with its low-voltage buffers is presented, which demonstrated megahertz switching at a power level of 270 W. The successful development of the VC-LJFET technology should hasten the introduction of SiC smart power ICs and eventually the system-on-a-chip applications in harsh environments.

1710-V 2.77-m/spl Omega/cm sub 2 4H-SiC trenched and implanted vertical junction field-effect transistors

This letter reports the design and fabrication of 4H-SiC bipolar junction transistors with both high voltage (>1kV) and high dc current gain (/spl beta/=32) at a collector current level of I/sub c/=3.83A (J/sub c/=319 A/cm/sup 2/). An Al-free base ohmic contact has been used which, when compared with BJTs fabricated with Al-based base contact, shows clearly improved blocking voltage. A specific on-resistance of 17 m/spl Omega//spl middot/cm/sup 2/ has been achieved for collector current densities up to 289 A/cm/sup 2/.

Development of 4H-SiC LJFET-Based Power IC

A high voltage 4H-SiC bipolar junction transistor (BJT) has been developed with 16 A, 600 V rating. This paper presents a new base drive structure for the SiC BJT for inverter application. The driver consists of one IGBT and one MOSFET to help turn-on and turn-off of the SiC BJT transistor in a Darlington like configuration. Instead of using conventional proportional current driven method for optimal driving bipolar transistor, the proposed base drive method can adaptively drive SiC BJT at near-saturated condition based on voltage balance of V/sub be/ and V/sub ce/. The IGBT and MOSFET gated transistor structure (IMGT) can significantly improve BJT switching behavior. Basic design principle is presented with simulation results. The proposed IMGT driver scheme is also verified by experimental results for both Si and SiC BJT. With the proposed driver scheme, the SiC BJT have the turn-on time of less than 0.5 /spl mu/s and turn-off time of less than 0.2 /spl mu/s under test condition of 300 V 15 A. Further work still needed for reducing conduction loss of SiC BJT.