Leontios Stampoulidis

10-Gb/s all-optical half-adder with interferometric SOA gates

In this letter, we report an all-optical module that generates simultaneously four Boolean operations at 10 Gb/s. The circuit employs two cascaded ultrafast nonlinear interferometers and requires only two signals as inputs. The first gate is configured as a 2 /spl times/ 2 exchange-bypass switch and provides OR and AND logical operations. The second gate generates XOR (SUM bit) and AND (CARRY bit) Boolean operations and constitutes a binary half-adder. Successful operation of the system is demonstrated with 10-Gb/s return-to-zero pseudorandom data patterns.

40-Gb/s All-Optical Processing Systems Using Hybrid Photonic Integration Technology

This paper presents an experimental performance characterization of all-optical subsystems at 40 Gb/s using interconnected hybrid integrated all-optical semiconductor optical amplifier (SOA) Mach-Zehnder interferometer (MZI) gates and flip-flop prototypes. It was shown that optical gates can be treated as generic switching elements and, when efficiently interconnected, can form larger and more functional network subsystems. Specifically, this paper reports on all-optical subsystems capable of performing on-the-fly packet clock recovery, 3R regeneration, label/payload separation, and packet routing using the wavelength domain. The all-optical subsystems are capable of operating with packet-mode traffic and are suitable for all-optical label-switched and self-routed network nodes. The intelligent functionality offered, combined with the compactness and stability of the optical gates, verifies the potential that all-optical technology can find application in future data-centric networks with efficient and dynamic bandwidth utilization. This paper also reports on the latest photonic integration breakthroughs as a potential migration path for reducing fabrication cost by developing photonic systems-on-chip utilizing multiple SOA-MZI optical gates on a single chip

Clock and data recovery circuit for 10-Gb/s asynchronous optical packets

We demonstrate an all-optical clock and data recovery circuit for short asynchronous data packets at 10-Gb/s line rate. The technique employs a Fabry-Perot filter and a SOA-based ultrafast nonlinear interferometer (UNI) to generate the local packet clock, followed by a second UNI gate to act as decision element, performing a logical AND operation between the extracted clocks and the incoming data packets. The circuit can handle short packets arriving at time intervals as short as 1.5 ns and arbitrary phase alignment.

Enabling Tb/s Photonic Routing: Development of Advanced Hybrid Integrated Photonic Devices to Realize High-Speed, All-Optical Packet Switching

We present recent advances in photonic integration introduced by integration-related European research project IST-MUFINS. The contribution of the project in the progress of a functional photonic integration is outlined, from device fabrication to device application focusing on photonic routing using multielement photonic chips. Specifically, we report on the transition from single-element to multielement photonic devices with the fabrication of hybrid integrated arrays of optical switches exploiting and upgrading the silica-on-silicon hybrid photonic integration. We demonstrate how the enhanced processing power and capacity of these components can be exploited to implement key functionalities required in next-generation fully integrated terabits per second photonic routers.

ARTEMIS: 40-gb/s all-optical self-routing node and network architecture employing asynchronous bit and packet-level optical signal processing

A 40-Gb/s asynchronous self-routing network and node architecture that exploits bit and packet level optical signal processing to perform synchronization, forwarding, and switching in the optical domain is presented. Optical packets are self-routed on a hop-by-hop basis through the network by using stacked optical tags, each representing a specific optical node. Each tag contains necessary control signals for configuring the node-switching matrix and forwarding each packet to the appropriate outgoing link and onto the next hop. In order to investigate the feasibility of their approach physical-layer simulations are performed, modeling each optical subsystem of the node showing acceptable signal quality and end-to-end bit error rates. In the All-optical self-RouTer EMploying bIt and packet-level procesSing (ARTEMIS) control plane, a timed/delayed resource reservation-based signaling scheme is employed combined with a load-balancing feedback-based contention-avoidance mechanism that can guarantee a high performance in terms of blocking probability and end-to-end delay

On-the-Fly All-Optical Contention Resolution for NRZ and RZ Data Formats Using Packet Envelope Detection and Integrated Optical Switches

We present a packet-by-packet contention resolution scheme that combines packet detection, optical space switching, and wavelength conversion performed in the optical domain by integrated optical switches. The packet detection circuit provides the control signals required to deflect and wavelength-convert the contending packets so that all the packets are forwarded to the same output without any collision or packet droppings. We demonstrate the compatibility of the scheme with both nonreturn-to-zero (NRZ) and return-to-zero (RZ) modulation formats by recording error-free operation for 10-Gb/s NRZ and 40-Gb/s RZ packet-mode traffic

Packet-format and network-traffic transparent optical signal processing

In this paper, we demonstrate optical transparency in packet formatting and network traffic offered by all-optical switching devices. Exploiting the bitwise processing capabilities of these optical transistors, simple optical circuits are designed verifying the independency to packet length, synchronization and packet-to-packet power fluctuations. Devices with these attributes are key elements for achieving network flexibility, fine granularity and efficient bandwidth-on-demand use. To this end, a header/payload separation circuit operating with IP-like packets, a clock and data recovery circuit handling asynchronous packets and a burst-mode receiver for bursty traffic are presented. These network subsystems can find application in future high capacity data-centric photonic packet switched networks.

The European BOOM Project: Silicon Photonics for High-Capacity Optical Packet Routers

During the past years, monolithic integration in InP has been the driving force for the realization of integrated photonic routing systems. The advent of silicon as a basis for cost-effective integration and its potential blend with III-V material is now opening exciting opportunities for the development of new, high-performance switching and routing equipment. Following this rationale, BOOM-as a European research initiative-aims to develop compact, cost-effective, and power-efficient silicon photonic components to enable optical Tb/s routers for current and new generation broadband core networks. This “siliconization” of photonic routers is expected to enable ultrahigh bit rates as well as higher levels of integration and power efficiency. The BOOM “device portfolio” includes all-optical wavelength converters, ultradense wave-division multiplexing (UDWDM) photodetectors, and high-speed transmitters; all based on silicon waveguide substrates. Here, we present the device concepts, the fabrication of photonic building blocks and the experiments carried out as the initial steps toward the realization of the first high-capacity silicon photonic router.

Contention Resolution for Burst-Mode Traffic Using Integrated SOA-MZI Gate Arrays and Self-Resetting Optical Flip-Flops

We demonstrate a photonic routing system that resolves the contention between bursty optical packets. The circuit is realized exclusively with integrated photonic components through the interconnection of semiconductor optical amplifier Mach-Zehnder interferometers gate arrays and optical flip-flops. The system resolves the contention - without burst segmentation - in the wavelength domain with a low power penalty ( < 1 dB).

First monolithic GaAs IQ electro-optic modulator, demonstrated at 150 Gbit/s with 64-QAM

We report on the first experimental demonstration of a GaAs IQ-modulator. Data rates of up to 150 Gbit/s are generated using QPSK, 16-QAM, 32-QAM and 64-QAM on a single carrier and polarization.