Li Hsien Yoong
University of Auckland
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Featured researches published by Li Hsien Yoong.
IEEE Transactions on Computers | 2009
Li Hsien Yoong; Partha S. Roop; Valeriy Vyatkin; Zoran Salcic
IEC 61499 has been endorsed as the standard for modeling and implementing distributed industrial process measurement and control systems. The standard prescribes the use of function blocks for designing systems in a component-oriented approach. The execution model of a basic function block and the manner for event/data connections between blocks are described therein. Unfortunately, the standard does not provide exhaustive specifications for function block execution. Consequently, multiple standard-compliant implementations exhibiting different behaviors are possible. This not only defeats the purpose of having a standard but also makes verification of function block systems difficult. To overcome this, we propose synchronous semantics for function blocks and show its feasibility by translating function blocks into a subset of Esterel, a well-known synchronous language. The proposed semantics avoids causal cycles common in Esterel and is proved to be reactive and deterministic under any composition. Moreover, verification techniques developed for synchronous systems can now be applied to function blocks.
international conference on industrial informatics | 2010
Matthew M. Y. Kuo; Li Hsien Yoong; Sidharta Andalam; Partha S. Roop
The IEC 61499 is an international standard for describing industrial process-control systems. Such systems typically consist of embedded computers that interact closely with physical processes within a feedback loop. In order to correctly control these physical processes, computations in response to inputs need to be done in a timely manner. A programs worst-case reaction time (WCRT) to inputs is usually used to ensure that timing constraints are met. Unfortunately, the standard has no provisions for specifying real-time constraints. Moreover, typical implementations of IEC 61499 are tightly coupled to their runtime environments—each with possibly different semantics and temporal properties—which makes it difficult to automate the estimation of their WCRTs. We propose to adopt a synchronous model for IEC 61499 programs. This allows the programs to be executed without the need of a run-time environment. Consequently, we are able to use a novel model-checking technique to estimate the WCRT of IEC 61499 programs. Experimental results on a suite of programs show that this approach provides conservative estimates that are, on average, less than 10 percent off from the actual WCRT.
ACM Transactions in Embedded Computing Systems | 2012
Li Hsien Yoong; Partha S. Roop; Zoran Salcic
Cyber-physical systems (CPS) are integrations of computation and control with sensing and actuation of the physical environment. Typically, such systems consist of embedded computers that monitor and control physical processes in a feedback loop. While modern electronic systems are increasingly characterized as CPS, their design and synthesis still rely on traditional methods, which lack systematic and automated techniques for accomplishment. Recently, IEC 61499 has been proposed as a standard for designing industrial process-control and measurement systems. It prescribes a component-based approach for developing industrial automation software using function blocks. Executable code can then be automatically generated and simulated from these function blocks. This bodes well for designers of CPS, who are more likely to be experts in specific industrial domains, rather than in computer science. The intuitive graphical nature and automatic code synthesis of IEC 61499 programs will alleviate the programming burden of industrial engineers, while ensuring more reliable software. While software synthesis from IEC 61499 programs is not new, the generation of efficient code from them has been wanting. This has made it difficult for function blocks to be used in software development for resource-constrained embedded controllers commonly employed in CPS. To address this, we present an approach that can generate very efficient code from function block descriptions. Experimental results from a benchmark suite shows that our approach produces substantially faster and smaller code compared to existing techniques.
IEEE Embedded Systems Letters | 2010
Li Hsien Yoong; Partha S. Roop
IEC 61499 is an international standard that prescribes the use of function blocks for designing industrial-process control systems. Function blocks enable control software to be developed using an intuitive standards-based graphical framework. The standard, however, lacks the semantic rigour necessary for automated verification of function block programs. Several approaches to fill this lacuna have been proposed, but these have so far focused on the verification of control properties by abstracting data from the program. This letter builds on a recent proposal to translate function blocks to Esterel in order to use the verification tools for Esterel to verify both control and data properties of function block programs. The key extensions to this translation are described herein, and have been implemented in a prototype tool. The viability of this approach is illustrated through several examples using this prototype. This demonstrates how a language with rigorous semantics and associated tools, like Esterel, can be advantageously combined with graphical notations familiar to industrial engineers to produce reliable control software.
international conference on industrial technology | 2009
Li Hsien Yoong; Partha S. Roop; Zoran Salcic
Current trends in the manufacturing sector have greatly increased the need for portability and reusability in software systems for industrial control and automation. The IEC 61499 standard has emerged out of this need for a platform-independent way to develop industrial control systems. So far, typical IEC 61499 solutions have relied on some run-time environment that differ in the execution model for each implementation. This has resulted in code that is neither portable, nor efficient in terms of execution speed and memory footprint. Therefore, we present, instead, a synchronous model for function blocks, which removes the need for a run-time environment by making all event scheduling decisions during compile-time. This approach has been used to create a function block compiler, with two different back-end code generators. We present experimental results of a benchmark suite implemented using different code generators for different execution models, and show that our technique yields significant gains in efficiency over existing approaches.
international conference on industrial informatics | 2007
Li Hsien Yoong; Partha S. Roop; Valeriy Vyatkin; Zoran Salcic
The IEC 61499 standard proposes a component-oriented approach for specifying industrial-process measurement and control systems using function blocks. Unfortunately, the standard does not provide rigorous semantics for the execution of function blocks, resulting in different behaviours on different implementations. The differences arise mostly as a result of the various event handling and scheduling mechanisms employed. To overcome such ambiguities, this paper proposes synchronous semantics for function block execution by translating function block programs into Esterel, a well-known synchronous language. The mathematical foundation of synchronous languages will not only precisely define the execution semantics, but also open up the pathway for formal verification of function blocks.
systems man and cybernetics | 2012
Li Hsien Yoong; Gareth Darcy Shaw; Partha S. Roop; Zoran Salcic
The IEC 61499 standard defines a generic architecture for designing distributed industrial control systems based on function blocks. The standard, however, lacks a formal model of computation to describe the behavior of function block compositions. While various models have been prescribed in the literature to define the composite behavior on a single computational node, few have been proposed to directly address compositions in a distributed setting. This paper proposes a globally asynchronous locally synchronous (GALS) model for distributed function block systems. The model provides an abstract way to view communication between function blocks without implying yet any particular implementation. This abstraction can then be subsequently refined to obtain various implementations with different tradeoffs. We do so using an approach that is fully compatible with the standards notion of communication function blocks, which abstract underlying communication mechanisms from the application. As a contribution, we have developed a compiler that automatically synthesizes separate programs for a given distributed function block system without needing any additional middleware or run-time environment to execute the resulting distributed code. The efficacy of the proposed approach is demonstrated through an industrial case study.
digital systems design | 2011
Simon Yuan; Li Hsien Yoong; Partha S. Roop
Esterel is a synchronous language suited for describing reactive embedded systems. It combines fine-grained parallelism with precise timing control for the execution of threads. Due to this, Esterel programs have typically been compiled into sequential code in software implementations, as tight synchronization between a large number of threads cannot be efficiently managed with an operating system (OS). This has enabled concurrent Esterel programs to be executed directly on single-core processors. Recently, however, multi-core processors have been increasingly used to achieve better performance in embedded applications. The conventional approach of generating sequential code from Esterel programs is unable to take advantage of multi-core processors. We overcome this limitation by compiling Esterel into a limited number of thread partitions (up to the number of available cores) to avoid the large overheads of implementing each Esterel thread separately within a conventional multithreading scheme. These partitions are then distributed onto separate cores using a static load balancing heuristic. The Esterel threads within a partition may then be dynamically scheduled with or without an OS. To evaluate the viability of this approach, we present experimental results comparing the execution of a set of benchmarks using one to four cores on the Intel Core 2 Quad with Linux, and one to two cores on the Xilinx Micro blaze without any OS. We have performed extensive benchmarking over large Esterel programs to illustrate that achieving throughput with parallel execution of Esterel is benchmark dependent.
Archive | 2015
Li Hsien Yoong; Partha S. Roop; Zeeshan E. Bhatti; Matthew M. Y. Kuo
This book describes a novel approach for the design of embedded systems and industrial automation systems, using a unified model-driven approach that is applicable in both domains. The authors illustrate their methodology, using the IEC 61499 standard as the main vehicle for specification, verification, static timing analysis and automated code synthesis. The well-known synchronous approach is used as the main vehicle for defining an unambiguous semantics that ensures determinism and deadlock freedom. The proposed approach also ensures very efficient implementations either on small-scale embedded devices or on industry-scale programmable automation controllers (PACs). It can be used for both centralized and distributed implementations. Significantly, the proposed approach can be used without the need for any run-time support. This approach, for the first time, blurs the gap between embedded systems and automation systems and can be applied in wide-ranging applications in automotive, robotics, and industrial control systems. Several realistic examples are used to demonstrate for readers how the methodology can enable them to reduce the time-to-market, while improving the design quality and productivity.
Eurasip Journal on Embedded Systems | 2009
Simon Yuan; Li Hsien Yoong; Sidharta Andalam; Partha S. Roop; Zoran Salcic
We propose a fully pipelined, multithreaded, reactive processor called STARPro for direct execution of Esterel. STARPro provides native support for Esterel threads and their scheduling. In addition, it also natively supports Esterels preemption constructs, instructions for signal manipulation, and a notion of logical ticks for synchronous execution. In addition to the reactive processors, we propose a new intermediate format called unrolled concurrent control-flow graph with surface and depth () that closely resembles the Esterel source. A compiler, based on , has been developed for code generation. We have synthesized STARPro and have carried out a range of benchmarking experiments. Experimental results reveal substantial improvement in performance and code size compared to software compilers. We also excel in comparison to recent reactive architectures, by achieving an average speed-up of 37% in worst-case reaction times and a speed-up of 38% in average-case reaction times. This has been achieved by utilizing fewer hardware resources, while incurring an average code size increase of 40%.