Li Xiaochun

An accurate RLGC circuit model for dual tapered TSV structure

A fast RLGC circuit model with analytical expression is proposed for the dual tapered through-silicon via (TSV) structure in three-dimensional integrated circuits under different slope angles at the wide frequency region. By describing the electrical characteristics of the dual tapered TSV structure, the RLGC parameters are extracted based on the numerical integration method. The RLGC model includes metal resistance, metal inductance, substrate resistance, outer inductance with skin effect and eddy effect taken into account. The proposed analytical model is verified to be nearly as accurate as the Q3D extractor but more efficient.

Analytical delay models for RLC interconnects under ramp input

Analytical delay models for Resistance Inductance Capacitance (RLC) interconnects with ramp input are presented for different situations, which include overdamped, underdamped and critical response cases. The errors of delay estimation using the analytical models proposed in this paper are less by 3% in comparison to the SPICE-computed delay. These models are meaningful for the delay analysis of actual circuits in which the input signal is ramp but not ideal step input.