Mao Junfa

An accurate RLGC circuit model for dual tapered TSV structure

A fast RLGC circuit model with analytical expression is proposed for the dual tapered through-silicon via (TSV) structure in three-dimensional integrated circuits under different slope angles at the wide frequency region. By describing the electrical characteristics of the dual tapered TSV structure, the RLGC parameters are extracted based on the numerical integration method. The RLGC model includes metal resistance, metal inductance, substrate resistance, outer inductance with skin effect and eddy effect taken into account. The proposed analytical model is verified to be nearly as accurate as the Q3D extractor but more efficient.

Analytical delay models for RLC interconnects under ramp input

Analytical delay models for Resistance Inductance Capacitance (RLC) interconnects with ramp input are presented for different situations, which include overdamped, underdamped and critical response cases. The errors of delay estimation using the analytical models proposed in this paper are less by 3% in comparison to the SPICE-computed delay. These models are meaningful for the delay analysis of actual circuits in which the input signal is ramp but not ideal step input.

Design of a 0.5 V CMOS cascode low noise amplifier for multi-gigahertz applications

This paper presents the design of 0.5 V multi-gigahertz cascode CMOS LNA for low power wireless communication. By splitting the direct current through conventional cascode topology, the constraint of stacking- MOS structure for supply voltage has been removed and based on forward-body-bias technology, the circuit can operate at 0.5 V supply voltage. Design details and RF characteristics have been investigated in this paper. To verify the investigation, a 0.5 V 5.4 GHz LNA has been fabricated through 0.18 m CMOS technology and measured. Measured results show that it obtains 9.1 dB gain, 3 dB NF with 0.5 V voltage and 2.5 mW power dissipation. The measured IIP3 is -3.5 dBm. Compared with previously published cascode LNA, it achieves the lowest supply voltage and lowest power dissipation with competitive RF performances.

A VLSI implementation of a low complexity Reed-Solomon encoder and decoder for CDPD

This paper presents VLSI implementation of an area efficient 8-error correcting (63,47) Reed-Solomon(RS) encoder and decoder for the CDPD (cellular digital packet data)communication systems. We implement this RS decoder using Euclidean algorithms which are regular, simple and naturally suitable for VLSI implementation. Constant multipliers based on certain composite fields are deployed in the encoder, which significantly decreases the encoders area. Multipliers over a certain composite field GF((2)2) adopted in this paper lower the complexity of the multiplication of the decoder. The RS encoder and decoder can independently operate at a clock frequency of 30 MHz. This chip was fabricated in 0.6/spl mu/m CMOS 1P2M technology with a supply of voltage of 5V, with die area 4mm /spl times/ 4mm. The chip has been fully tested and stratifies the demand of the CDPD communication systems.