Li-Yi Peng

Analysis of the Back-Gate Effect in Normally OFF p-GaN Gate High-Electron Mobility Transistor

This paper discusses the impact of the back-gate bias on the dc, low-frequency noise, and dynamic behavior characteristics of a p-GaN gate high-electron mobility transistor on silicon substrate. This paper is investigated to understand the physical mechanisms of the back-gate terminal modulation of normally OFF GaN power devices. When a negative backgate bias VB voltage is applied, the 2-D electron gas channel will get closer to AlGaN/GaN heterointerface and interface scattering, such as interface roughness and alloy-disorder scattering will increases significantly, which may be responsible for the increased ON-state resistance (RON). Meanwhile, the opportunity for the capture of carriers by deep-level traps is reduced and the low-frequency noise is thereby suppressed. Under positive VB bias, RON can be reduced but, according to capacitance-voltage measurements and carrier fluctuations extracted from the low-frequency noise spectra, the transported carriers are obviously trapped by the deep-level.

Electrical characterization of a gate-recessed AlGaN/GaN high-electron-mobility transistor with a p-GaN passivation layer

A novel passivation technique was developed that reduces the electron-surface-hopping-induced leakage current of AlGaN/GaN high-electron-mobility transistors (HEMTs) and enhances their electrical properties under high drain bias operation. The key aspect of this passivation technique entailed growing a p-type GaN layer on a traditional depletion-mode AlGaN/GaN HEMT; this p-GaN passivation layer was also used as the spacer layer of a field-plate metal. The originally exposed gate-to-source and gate-to-drain areas were passivated by the p-GaN cap layer. Thus, a surface depletion region was formed between the p-GaN passivation layer and an n-type AlGaN/GaN two-dimensional electron gas channel. This extra surface depletion region depleted the channel carriers far from the surface to reduce the probability of the carriers being trapped by surface defects. Therefore, the carrier-hopping-induced leakage current in the gate-to-drain area, which was strongly temperature-dependent, was suppressed. Low-frequency noi...

Temperature dependency and reliability of through substrate via InAlN/GaN high electron mobility transistors as determined using low frequency noise measurement

The reliability of a InAlN/GaN/Si high electron mobility transistor device was studied using low frequency noise measurements under various stress conditions. By applying the through substrate via (TSV) technology beneath the active region of the device, buffer/transition layer trapping caused by the GaN/Si lattice mismatch was suppressed. In addition, a backside SiO2/Al heat sink material improved thermal stability and eliminated the vertical leakage current of the proposed device. Applying the TSV technology improved the subthreshold swing slope from 260 to 230 mV/dec, owing to the stronger channel modulation ability and reduced leakage current of the device. The latticed-matched InAlN/GaN heterostructure had a stable performance after high current operation stress. The suppression of buffer/transition layer traps of the TSV device is a dominant factor in device reliability after long-term high-electric-field stress.

Normally-off matrix layout p-GaN gate AlGaN/GaN power HEMT with a through-substrate via process

Normally-off p-GaN gate AlGaN/GaN high electron mobility transistor (HEMT) on Si substrate with matrix heat redistribution layer (RDL) and through substrate via (TSV) technologies was investigated. Compared to traditional power cell design, the modified matrix heat RDL provides a circular arc layout together with an extra drain pad to reduce rectangular layout induced leakage current and the device total current density was also enhanced. In addition, TSV process beneath the GaN power HEMT active region spreads the heat efficiently and the lattice mismatch induced traps in transition/buffer layer were also removed. Based on the measured results analysis of dynamic RON to DC RON (RDC), the removal of lossy substrate in TSV is also beneficial for improving device switching behavior. Therefore, a high switching speed normally-off GaN power HEMTs together with a superior thermal management was proposed in this study.

Enhancement/Depletion-mode AlGaN/GaN HEMTs demonstration using partial p-type GaN gate etching process

In this work, we design a 70nm Mg doped GaN stacked on standard GaN HEMTs structure, the concentration is 5×1019 cm3. The enhancement mode GaN HEMTs was sequential manufactured following by standard semiconductor procedure. The Vth, maximum Ids, and gm peak were +0.8V, 242.3 mA/mm, and 45.3 mS/mm, respectively. Low frequency noise, C-V measurement, and pulse measurement were analyzed to comprehend this device.

Effects of the Fe-doped GaN buffer in AlGaN/GaN HEMTs on SiC substrate

AlGaN/GaN high electron mobility transistors (HEMTs) with a Fe-doped GaN buffer on a SiC substrate were presented for power switching applications. In order to investigate the effects of an Fe-doped GaN buffer on device characteristics, HEMT devices with an Fe-doped GaN buffer on SiC were fabricated alongside with the conventional devices utilizing an unintentionally doped (UID) u-GaN buffer on SiC, and compared their device characteristics. The charge-injection-type hysteresis voltage shift ΔV of 42mV is observed in the C-V loop measurement, after the insertion of the Fe-doped HEMT as gate metal layer. The voltage shift ΔV of the u-GaN HEMT was 0.03mV. It shows that the Fe doping increases the trap at GaN buffer. However the off-state breakdown behavior of Fe-GaN (VBV=195V) was better than u-GaN (VBV=148V). The RF performance of Fe-GaN, the current gain cutoff frequency (fT) of 5.4GHz and fmax of 15.4GHz, also higher than the ft=4.2GHz and an fmax=13.4GHz of the u-GaN HEMT. Its shown that Fe-GaN has potential for high power and high frequency transistors.