Feng-Tso Chien

Nitrogen-vacancy-related defects and Fermi level pinning in n-GaN Schottky diodes

The relationship between the surface states related to nitrogen-vacancy defects and surface Fermi level pinning has been investigated using x-ray photoelectron spectroscopy and capacitance–voltage measurements. Barrier heights of 1.09, 0.50, 1.20, and 0.50 eV, respectively, were obtained for Ni/(NH4)2Sx-treated n-GaN, Ni/etched n-GaN, Au/(NH4)2Sx-treated n-GaN and Au/etched n-GaN Schottky diodes. For Schottky diodes treated with (NH4)2Sx, the observed Schottky barrier height is very close to the Schottky limit, due to the reduction of the surface state density. This also suggests that a large number of surface states related to nitrogen-vacancy defects in the etched n-GaN surface would lead to the pinning of the Fermi level at 0.50 eV below the conduction band edge.

Improved device linearity of AlGaAs/InGaAs HFETs by a second mesa etching

The conventional mesa isolation process in AlGaAs/InGaAs heterostructure FETs results in the gate contacting the exposed highly doped region at the mesa sidewalls, forming a parasitic gate leakage path. In this work, we suppress the gate leakage from the mesa-sidewall and enhance microwave power performance by performing an additional second mesa etching. The device gate leakage characteristics under high-input power swing are particularly investigated to reveal an improvement in device linearity, which is sensitive to the sidewall gate leakage. This modified device (M-HFETs) provides not only a higher linear RF output power but also a lower IM3 product than those characteristics in conventional HFETs.

Characteristics of AlGaN/GaN HEMTs With Various Field-Plate and Gate-to-Drain Extensions

AlGaN/GaN high-electron-mobility transistors (HEMTs) with various field-plate (FP) and gate-to-drain distance extensions are fabricated and investigated. Experiments are carried out on 20 transistors. Their ON-state resistance (RON), OFF-state breakdown voltage (VBR), RF performance, and low-frequency noise are measured and studied. The FP extension is found to significantly improve the OFF-state breakdown voltage. However, the FP extension obviously weakens the frequency response and power added efficiency performance, because it increases the feedback Cgd. The FP extension is beneficial to the reduction of the electric field intensity at the gate edge of the device and reduces the probability of the injection of electrons into traps, resulting in the reduction of low- frequency noise.

Investigation of degradation for ohmic performance of oxidized Au/Ni/Mg-doped GaN

The mechanism of ohmic contact degradation for the oxidized Au/Ni/Mg-doped GaN under various annealing times has been investigated. According to the results from x-ray photoelectron spectroscopy and the Cserveny’s concept, we found that an increase of hole concentration of NiOx would lead to the increasing barrier height and the increasing specific contact resistance (ρc) of oxidized Au/Ni/Mg-doped GaN. This suggests that the NiOx plays an important role in increasing (or reducing) the ρc of oxidized Au/Ni/Mg-doped GaN.

Characterization of enhancement-mode AlGaN/GaN high electron mobility transistor using N2O plasma oxidation technology

In this study, an enhancement-mode (E-mode) AlGaN/GaN high electron mobility transistor (HEMT) using N2O plasma oxidation process has been performed. Before the gate metal deposition, the AlGaN barrier layer was treated by 135 W N2O plasma for 240 s. The surface native oxide of AlGaN was removed and a 4 nm high quality Ga2O3/Al2O3 compound insulator was simultaneously formed. The threshold voltage of conventional depletion-mode (D-mode) GaN HEMT was −3.6 V and this value can be shifted to +0.17 after N2O plasma oxidation treatment beneath the gate metal. This 4 nm Ga2O3/Al2O3 compound insulator oxidized by N2O can suppress the polarization charge density for E-mode operation of gate terminal and the gate leakage was also reduced simultaneously.

A Kink-Effect-Free Poly-Si Thin-Film Transistor With Current and Electric Field Split Structure Design

In this paper, we propose a high-performance kink-effect-free bottom-gated polycrystalline (poly-Si) thin-film transistor with a drain-extended field plate (FP) structure. The extended-drain FP can distribute the electric field to the channel near the drain area and, particularly, can change the electron current path. The altered current path leads to a high current density and high electric field split structure that reduces the impact ionization at the drain area. Our experimental results show that the on-current of the proposed device is higher than that of the conventional structure, and the kink effect as well as the leakage current is simultaneously improved. Moreover, the device stability, such as threshold voltage shift and transconductance degradation under a high gate bias, is enhanced by the proposed drain-extended FP design. The current and electric field split structure is also beneficial in scaling down the device size for a better performance.

Induced changes in surface band bending of n-type and p-type AlGaN by oxidation and wet chemical treatments

The surface chemistry and electrical properties of p-type and n-type AlGaN surfaces were studied via x-ray photoelectron spectroscopy before and after oxidation and wet chemical treatments. Shifts in the surface Fermi level were measured with the change in onset of the valence-band spectra. Oxidation and HF and (NH4)2Sx treatments on p-type AlGaN (n-type AlGaN) led to an increase (the reduction) in the surface band bending due to more N vacancies and N vacancies being occupied by S (i.e., donorlike states) than Al vacancies and Ga vacancies (i.e., acceptorlike states) near the p-type AlGaN (n-type AlGaN) surface region. The changes in surface chemistry indicate that oxidation and wet chemical treatments alter the surface state density through the formation of more donorlike states.

Poly Si Nanowire Thin Film Transistors With Vacuum Gap Design

Via a simple selective-etching technique, a poly Si nanowire (NW) thin-film transistor (TFT), accompanied with the offset region, embedded vacuum gaps, and subgate structure, has been fabricated and characterized. The embedded vacuum gaps serves as an effective thicker insulator above the offset region, thus effectively reduces OFF-state leakage current and kink effect. This is because, under gate/drain biases, the electric field at channel surface near the drain can be reduced by the vacuum gap design compared with that in the conventional NW TFT. The extension of TiN layer above vacuum gap serves as a subgate and induces an inversion layer at the offset region to maintain a high on-current. The local electrical field located at the channel spacer surface and sharp corner near the drain is much lower in proposed vacuum gap structure compared with that in conventional NW TFT. Therefore, the device reliability, such as the degradation of threshold voltage, subthreshold swing, and transconductance under dc hot-carrier stress, is obviously improved by the proposed vacuum gap structure. Therefore, this proposed NW TFT is suitable for applications in advanced system-on-panel and 3-D circuit.

A Novel Self-Aligned Double-Channel Polysilicon Thin-Film Transistor

In this paper, a high-current self-aligned double-channel polycrystalline silicon thin-film transistor (SA-DCTFT) is proposed, demonstrated, and analyzed. This self-aligned device, which includes two channels, a nitride spacer, two offset-gated structures, and a raised source/drain (RSD) region, reveals better device performance. In addition, the top and bottom channels of the proposed device are self-aligned, and no extra mask is needed as compared with the conventional double-channel devices. Our experimental results show that the on-current of the SA-DCTFT is about twice higher than that of the conventional structure, and the leakage current and kink effect are considerably reduced simultaneously. Moreover, the device stability, such as threshold voltage shift and current degradation under a high gate bias, is enhanced by the proposed self-aligned double channels, nitride spacer, offset-gated structures, and RSD design. The lower drain electric field of the SA-DCTFT is also benefitted to the device scaling down for better performance.

RIE gate-recessed (Al/sub 0.3/Ga/sub 0.7/)/sub 0.5/In/sub 0.5/P/InGaAs double doped-channel FETs using CHF 3 +BCl 3 mixing plasma

BCl/sub 3/+CHF/sub 3/ gas mixtures for the reactive ion etching process were applied to the gate-recess for fabricating (Al/sub 0.3/Ga/sub 0.7/)/sub 0.5/In/sub 0.5/P quaternary heterostructure double doped-channel FETs (D-DCFET), where a high uniformity of Vth was achieved. With the merits of this wide bandgap (Al/sub 0.3/Ga/sub 0.7/)/sub 0.5/In/sub 0.5/P layer, microwave power performance of this heterostructure D-DCFET demonstrates a compatible performance for devices fabricated on AlGaAs/InGaAs heterostructures.