Li Yubai

Error Correcting Cyclic Redundancy Checks based on Confidence Declaration

Cyclic redundancy check is one of the most popular methods of error detection for digital signals, whereas it has not the inherent capability of correcting multi-bit errors and most of the existing works focus on algorithm optimization of CRC. Take example for the Mode S downlink error correction, this paper investigates two multi-bit error correction techniques using cyclic redundancy checks based on bit and confidence declaration and presents a combined process flow for correcting both burst and random errors. Both techniques enhance the error correction capability of cyclic redundancy check while not adding more redundancy

A Practical FMCW Radar Signal Processing Method and Its System Implementation

Frequency modulated continuous wave (FMCW) radar system measures objects and acquires information by changing the sending signal frequency along with the time and by measuring the receiving signals frequency with respect to the sending signals. This paper introduces a practical FMCW radar signal processing method and system. This system is mainly used for eliminating noise interference from the sampled signal, checking out the objective signal, and sending the data as the processing results to a computer through the PCI Interfaces. The results are finally processed by the computer and displayed on its screen. This paper analyzes the signal processing algorithm, and applies it to the system implementation. This processing system uses the universal DSP chip as the core device, thus making it easier to use and transplant. This system can be applied to many fields (mini near-distance radar, aircraft carried radar, etc) as long as the front antenna and transceiver system are well organized. It can also be applied to the vehicle carried radar for distance-measuring

Design and simulation of a Torus topology for network on chip

Abstract Aiming at the applications of NOC (network on chip) technology in rising scale and complexity on chipsystems, a Torus structure and corresponding route algorithm for NOC is proposed. This Torus structure improvestraditional Torus topology and redefines the denotations of the routers. Through redefining the router denotationsand changing the original router locations, the Torus structure for NOC application is reconstructed. On the basisof this structure, a dead-lock and live-lock free route algorithm is designed according to dimension increase. SystemC is used to implement this structure and the route algorithm is simulated. In the four different traffic patterns, average, hotspot 13%, hotspot 67% and transpose, the average delay and normalization throughput of this Torusstructure are evaluated. Then, the performance of delay and throughput between this Torus and Mesh structure iscompared. The results indicate that this Torus structure is more suitable for NOC applications.

A fast time acquisition method for PSK-2DSS systems

A fast time acquisition method for PSK-2DSS systems is presented in this paper. By analyzing the structure characteristics of the two dimensional spread spectrum sequence, the redundant operations hidden in traditional time correlation method were found. Then, a novel two-stage acquisition method is proposed, aiming mainly at removing the reduplicate multiply operations in the correlation processing. In this two-stage method, the former stage performs some data rearranging operations, on the basis of the estimate values of the initial phases of the two spreading codes. Then in the latter stage, the rearranged data is time correlated with the local version of the first code, and the result is used to verify whether the estimate is right. The data rearranging breaks through the coherent integration length limit in the serial search acquisition. So the proposed method can achieve much higher acquisition sensitivity than the serial search based and is more suitable for weak signals acquisition. Actually, since the data rearranging only adjusts the computation flow and no information will be lost, the proposed method has the same performance as the traditional time correlation. Benefited from the data rearranging, however, many multiply operations in the correlation processing can be combined. Then the computational complexity is reduced dramatically, and the acquisition can be accomplished very efficiently. At the end of this paper, numerical examples confirm the effectiveness of the proposed method.

Real-Time data and confidence declaration algorithm for MSSR Reply

This paper presents a kind of method which can extract reply of mono-pulse secondary surveillance radar (MSSR) effectively at high density reply and introduce the real-time algorithm of confidence analyzing on the reply code. This arithmetic can not only extract code and confidence of the pulse reply code a time, but also fulfil the OVERLAP and de-FTUTI processing. The reply differentiation and confidence estimation can be correctly confirmed when there is multi-target reply-blend, providing available report form of the target trace

Anti-Jamming Process for Reply Extraction of MSSR

This paper is about MSSR reply decoding and confidence bits. A novelty method is presented in this paper which can extract the reply code efficiently on highly high density reply occasion. The results of theoretical analysis and practical system-test have showed that this method can get very high detection probability and very low falsehood probability even in the environment of high density inquiring and complex jamming of FRUIT

Network on Chip: Key Communication Technology in MP-SoC

As the development of deep sub-micron (DSM) technique, integration of more communication applications and processing modules in one single chip is becoming feasible. MP-Soc, as an advacned SoC, has strong abilities in processing, software-hardware cooperation. It is widely used in many applications. The development of MP-SoC is far behind the present technology and technique. The bottleneck of MP-SoC is the low communication efficiency of resouces based on bus architecture. The paper studies NoC, the newest communication technology on chip. Summarizes the present studies, points out some key directions in NoC study, with detailed analysis, and designs an experimental platform system for NoC simulation, specificly for MP-SoC. The paper originates from a NoC project, which is supported by National Natural Science Foundation of China