Liang Renrong

A PNPN tunnel field-effect transistor with high-k gate and low-k fringe dielectrics

A PNPN tunnel field effect transistor (TFET) with a high-k gate dielectric and a low-k fringe dielectric is introduced. The effects of the gate and fringe electric fields on the TFETs performance were investigated through two-dimensional simulations. The results showed that a high gate dielectric constant is preferable for enhancing the gate control over the channel, while a low fringe dielectric constant is useful to increase the band-to-band tunneling probability. The TFET device with the proposed structure has good switching characteristics, enhanced on-state current, and high process tolerance. It is suitable for low-power applications and could become a potential substitute in next-generation complementary metal-oxide-semiconductor technology.

Epitaxy of GaAs thin film with low defect density and smooth surface on Si substrate

Device-quality GaAs thin films have been grown on miscut Ge-on-Si substrates by metal-organic chemical vapor deposition. A method of two-step epitaxy of GaAs is performed to achieve a high-quality top-layer. The initial thin buffer layer at 360 °C is critical for the suppression of anti-phase boundaries and threading dislocations. The etch pit density of GaAs epilayers by KOH etching could reach 2.25 × 105 cm−2 and high-quality GaAs top epilayers are observed by transmission electron microscopy. The band-to-band photoluminescence property of GaAs epilayers on different substrates is also investigated and negative band shifts of several to tens of meVs are found because of tensile strains in the GaAs epilayers. To achieve a smooth surface, a polishing process is performed, followed by a second epitaxy of GaAs. The root-mean-square roughness of the GaAs surface could be less than 1 nm, which is comparable with that of homo-epitaxial GaAs. These low-defect and smooth GaAs epilayers on Si are desirable for GaAs-based devices on silicon substrates.

Effective interface passivation of a Ge/HfO2 gate stack using ozone pre-gate treatment and ozone ambient annealing

The physical and electrical properties of a Ge/GeO2/HfO2/Al gate stack are investigated. A thin interfacial GeO2 layer (~1 nm) is formed between Ge and HfO2 by dual ozone treatments, which passivates the Ge/high-k interface. Capacitors on p-type Ge substrates show very promising capacitance-voltage (C—V) characteristics by using in situ pre-gate ozone passivation and ozone ambient annealing after high-k deposition, indicating efficient passivation of the Ge/HfO2 interface. It is shown that the mid-gap interface state density atthe Ge/GeO2 interface is 6.4 × 1011 cm−2 eV−1. In addition, the gate leakage current density of the Ge/GeO2/HfO2/Al gate stack passivated by the dual ozone treatments is reduced by about three orders of magnitude compared to that of a Ge/HfO2/Al gate stack without interface passivation.

Fermi level depinning by a C-containing layer in a metal/Ge structure by using a chemical bath

Insertion of a C-containing layer in a metal/Ge structure, using a chemical bath, enabled the Schottky barrier height (SBH) to be modulated. Chemical baths with 1-octadecene, 1-hexadecene, 1-tetradecene, and 1-dodecene were used separately with Ge substrates. An ultrathin C-containing layer stops the penetration of free electron wave functions from the metal to the Ge. Metal-induced gap states are alleviated and the pinned Fermi level is released. The SBH is lowered to 0.17 eV. This new formation method is much less complex than traditional ones, and the result is very good.

Electrical properties and temperature behavior of strained-Si N-MOSFETs

Strained-Si n-MOSFET transistors were fabricated on strained Si/uniform relaxed Si0.9Ge0.1/relaxed graded SiGe/Si substrate using reduced pressure chemical vapor deposition (RPCVD) technique. The transistors show a significant mobility enhancement of ~50% compared to control Si n-MOSFET mobilities at low vertical field and at room temperature. The drain current is increased by ~40% for long channel devices. The temperature behavior including the variation of the inversion layer mobility, the threshold voltage shifts and the reduction of saturated drain current, has been investigated for operating temperatures ranging from room temperature to 70degC compared with strained-Si and Si control n-MOSFET transistors. It was found that the electron mobility has the largest enhancement around room temperature