Ligang Hou

Impedance Adapting Compensation for Low-Power Multistage Amplifiers

A power-efficient frequency compensation topology, Impedance Adapting Compensation (IAC), is presented in this paper. This IAC topology has, on one hand, a normal Miller capacitor, which is still needed to provide an internal negative feedback loop, and on the other hand, a serial RC impedance as a load to the intermediate stage, improving performance parameters such as stability, gain-bandwidth product and power dissipation. A three-stage IAC amplifier was implemented and fabricated in a 0.35 μm CMOS technology. Experiment results show that the implemented IAC amplifier, driving a 150 pF load capacitance, achieved a gain-bandwidth product (GBW) of 4.4 MHz while dissipating only 30 μW power with a 1.5 V supply.

Comparison Research between XY and Odd-Even Routing Algorithm of a 2-Dimension 3X3 Mesh Topology Network-on-Chip

The Network-on-Chip (NoC) has been recognized as a paradigm to solve System-on-Chip (SoC) design challenges. The routing algorithm is one of key researches of a NoC design. XY routing algorithm, which is a kind of distributed deterministic routing algorithms, is simple to be implemented. Odd-Even (OE) routing algorithm, whose implementation is complex, is a sort of distributed adaptive routing algorithms with deadlock-free ability. We demonstrate the two routing algorithms in details at first. XY routing algorithm and OE routing algorithm are then simulated and compared based on a 3X3 mesh topology NoC with NIRGAM simulator. The simulation results show that OE routing algorithm, whose P parameter equals to 1.09, increases P parameter greatly as compared to XY routing algorithm, whose P parameter equals to 0.86, in a 2-dimension 3X3 mesh topology NoC, with Constant Bit Rate (CBR) traffic condition of each tail.

Implementation of GSM SMS remote control system based on FPGA

A design of a GSM SMS(Short Message Service) remote appliance control system based on FPGA is completed in this paper. The paper based on the original telephone remote control system, mainly designs a remote appliance control system using the GSM SMS to finally achieve the dual-mode control of phone and SMS control, which makes the remote appliance control system more perfect. As the control core, FPGA enables this system to be nimble to dispose and have an extended function. The main works completed in this paper include hardware module design (GSM SMS module, RS232 interface module, and the temperature monitor module), FPGA logic design, and system board-level verification. The testing result indicates that the designed long-distance electrical control system meets the designing goal and has application potential.

Leakage current, active power, and delay analysis of dynamic dual Vt CMOS circuits under P-V-T fluctuations

Abstract The leakage current, active power and delay characterizations of the dynamic dual V t CMOS circuits in the presence of process, voltage, and temperature ( P – V – T ) fluctuations are analyzed based on multiple-parameter Monte Carlo method. It is demonstrated that failing to account for P – V – T fluctuations can result in significant reliability problems and inaccuracy in transistor-level performance estimation. It also indicates that under significant P – V – T fluctuations, dual V t technique (DVT) is still highly effective to reduce the leakage current and active power for dynamic CMOS circuits, but it induces speed penalty. At last, the robustness of different dynamic CMOS circuits with DVT against the P – V – T fluctuations is discussed in detail.

Neural Network Based VLSI Power Estimation

This paper forwards a neural network based method on VLSI power estimation. Power estimation technique was a tradeoff between precision and time. Simulation based power estimation gave the most accurate result but time consuming. Monte-Carlo and other statistical approaches estimated VLSI power in a less simulation dependent way and got accurate result using less time. This paper used neural network to perform VLSI power estimation. Experiments were made on ISCAS89 benchmark. Power estimation results from Murugavel, et al., 2002 and Bhanja, S and Ranganathan, N, 2003 were used as training or target vector. Different net structure, training plans and vector organizations were applied. For limited number of test vector (number of benchmark circuits), limited experimental results showed the neural network based power estimation method could give acceptable results with specific net structure. Power estimation runs faster. Linear regression is used to evaluate neural net. Probabilistic results of regression R-value are observed. Analysis shows that unfolded regression R-value sample fit normal distribution. This method can achieve a much faster power estimation result of VLSI on I/O and gate information without simulation and analysis of detail structure and interconnections

Domino gate with modified voltage keeper

Using both the modified supply voltage and body voltage, an optimized keeper technique is presented in this paper to tradeoff the performance of domino OR gates. The simulation results show that the novel technique can highly improve power/speed efficiency and robustness to noise. In addition, because of employment of body biased voltage, the optimized keeper technique enables to minimize effect of the strong process parameter variation.

Using charge self-compensation domino full-adder with multiple supply and dual threshold voltage in 45nm technology

A charge self-compensation technique, based on P-type logic dynamic node charging to N-type logic dynamic node, is proposed in this paper. A novel Zipper CMOS domino full-adder is implemented using this technique, dual threshold voltage technique, and multiple supply technique for power reduction. A power distribution simulation running indicates that the active power of the implemented full-adder can be reduced by up to 37%, 5% and 7%, and its leakage power can be reduced by up to 41%, 20% and 43% as compared to the standard, the dual threshold voltage, and the multiple supply Zipper CMOS domino full-adder with similar delay time, respectively. At last, the influence of the combination idle state determined by inputs and clock signals on the leakage current is analyzed and the optimal idle state is obtained.

TSV based 3D IC wire length calculation algorithm

This paper forwards a novel wire length calculation algorithm based on TSV position. Typical 2D wire length calculation method such as half-perimeter model does not take via position into account. But in 3D IC placement, TSV position does affect the real wire length which is ignored in previous works. To get accurate wire length data and help 3D placement researches, this paper forwards the TSV based 3D IC wire length algorithm. Experiments are done on folded placement results of IBM placement benchmark circuits. Results shows that this algorithm can effectively identify the difference wire length of the cross wafer net according to the traditional method and calculate it accurately.

Application of PSO-adaptive neural-fuzzy inference system (ANFIS) in analog circuit fault diagnosis

In order to solve the problem of fault diagnosis method for analog IC diagnosis, the method based on Adaptive Neural-fuzzy Inference System (ANFIS) is proposed. Using subtractive clustering and Particle Swarm Optimization (PSO)-hybrid algorithm as a tool for building the fault diagnosis model, then, the model of fault diagnosis system was used to the circuit fault diagnosis. Simulation results have shown that the method is more effective.

A Network on Chip Architecture and Performance Evaluation

Networks-on-chip (NoCs) have emerged as an alternative to ad-hoc wiring or bus-based global interconnection in Systems-on-Chip (SoCs). The architecture of network significantly determines system performance. This paper proposes a network on chip architecture with 2-demention mesh topology, odd-even routing algorithm, wormhole switching technique and only input buffers. The size of packet is 20 bytes and that of flit is 5 bytes. The performance of proposed architecture is evaluated based on metrics of latency and throughput per channel under Constant Bit Rate (CBR) and Bursty traffic. For the proposed architecture, the evaluation results reveal that the average latency of whole network channels is 1.97 cycles under CBR traffic and 1.92 cycles under Bursty traffic. The average throughput of whole network channels is 8.8555 Gbps under CBR traffic and 8.8212 Gbps under Bursty traffic.