Na Gong

Ultra-Low Voltage Split-Data-Aware Embedded SRAM for Mobile Video Applications

This brief presents an ultra-low voltage split-data-aware 10T and 8T (SDA-10T-8T) embedded static random access memory (SRAM) design for MPEG-4 video processors. Without additional complex peripheral circuits, the proposed design enables a reliable operation at 0.36 V under process variation and aging effect. The experimental results based on 45-nm CMOS technology show that, as compared to conventional SRAM design, our proposed design can achieve a 95% reduction in active power, with no significant degradation in frame quality. In addition, the proposed design suppresses the leakage current effectively, thereby reducing the leakage induced bitline voltage drop rate from 1.54 mV/ns to 0.64 mV/ns at Vdd = 0.36 V.

Leakage current, active power, and delay analysis of dynamic dual Vt CMOS circuits under P-V-T fluctuations

Abstract The leakage current, active power and delay characterizations of the dynamic dual V t CMOS circuits in the presence of process, voltage, and temperature ( P – V – T ) fluctuations are analyzed based on multiple-parameter Monte Carlo method. It is demonstrated that failing to account for P – V – T fluctuations can result in significant reliability problems and inaccuracy in transistor-level performance estimation. It also indicates that under significant P – V – T fluctuations, dual V t technique (DVT) is still highly effective to reduce the leakage current and active power for dynamic CMOS circuits, but it induces speed penalty. At last, the robustness of different dynamic CMOS circuits with DVT against the P – V – T fluctuations is discussed in detail.

cNV SRAM: CMOS Technology Compatible Non-Volatile SRAM Based Ultra-Low Leakage Energy Hybrid Memory System

A CMOS technology compatible non-volatile SRAM (cNV SRAM) is proposed in this paper to achieve energy efficient on-chip memory. cNV SRAM works as conventional 8T SRAM to keep high speed in work mode; in sleep mode, it backs up the data in its NV component and switches off the power supply, thereby minimizing the leakage energy without data loss. The circuit- and architectural- level implementation schemes of cNV SRAM are developed considering multiple key performance parameters including energy dissipation, access time, write time, noise margin, layout area, restoration time, and injection charges. Simulation results on SPEC 2000 benchmark suite demonstrate that cNV SRAM realizes 86 percent energy savings on average with negligible performance impact and small hardware overhead as compared to conventional SRAM. Finally, the impact of the sleep time and memory size on the effectiveness of cNV SRAM is analyzed in detail and it shows that cNV SRAM is particularly effective to implement large on-chip memories with long idle time.

Variation Aware Sleep Vector Selection in Dual V t Dynamic OR Circuits for Low Leakage Register File Design.

Dual threshold voltage (Vt) technique is applied widely in dynamic OR circuits to achieve low leakage in register files (RF) design, but its effectiveness is significantly influenced by the selected sleep vector during the standby mode. As technology scales into deep nanometer era, the sleep vector selection in dual Vt dynamic OR (DV-OR) circuits becomes challenging due to the impact of PVT (process, supply voltage and temperature) variations. In this paper, we analyze the relationship among PVT variations, leakage characteristics, and sleep vectors in DV-OR circuits. We further perform a comprehensive study on sleep vector selection and explore its design space in DV-OR circuits. Finally, we present a generalization of our analysis for multiple Vt dynamic OR circuits and provide sleep vector selection guidelines to achieve low leakage and robust register files in modern processors.

Variation-and-aging aware low power embedded SRAM for multimedia applications

This paper presents a low power embedded SRAM memory design for MPEG-4 video processors. Considering both of the process variation and aging effect, the proposed design adopts an optimal high voltage for spatial voltage scaling to achieve high power efficiency. Simulations in FreePDK 45nm CMOS technology show that our proposed technique can achieve 85%, 90%, and 79% reduction in write power, read power, and leakage current, respectively, with graceful degradation (~5.6%) in video quality, as compared to conventional SRAM design.

Optimization and predication of leakage current characteristics in wide domino OR gates under PVT variation

The leakage current characteristics of wide dual Vt domino OR gates is studied and gate-level models for estimating sub-threshold leakage and gate leakage current with two different sleep states are developed to determine the optimal sleep state. Results demonstrate that the developed models are robust and exhibit maximum error of 4% with respect to device-level BSIM4 models based HSPICE simulations. Furthermore, PVT variation aware leakage current characteristics of domino OR gates is analyzed and the optimal sleep state is obtained.

Domino gate with modified voltage keeper

Using both the modified supply voltage and body voltage, an optimized keeper technique is presented in this paper to tradeoff the performance of domino OR gates. The simulation results show that the novel technique can highly improve power/speed efficiency and robustness to noise. In addition, because of employment of body biased voltage, the optimized keeper technique enables to minimize effect of the strong process parameter variation.

Using charge self-compensation domino full-adder with multiple supply and dual threshold voltage in 45nm technology

A charge self-compensation technique, based on P-type logic dynamic node charging to N-type logic dynamic node, is proposed in this paper. A novel Zipper CMOS domino full-adder is implemented using this technique, dual threshold voltage technique, and multiple supply technique for power reduction. A power distribution simulation running indicates that the active power of the implemented full-adder can be reduced by up to 37%, 5% and 7%, and its leakage power can be reduced by up to 41%, 20% and 43% as compared to the standard, the dual threshold voltage, and the multiple supply Zipper CMOS domino full-adder with similar delay time, respectively. At last, the influence of the combination idle state determined by inputs and clock signals on the leakage current is analyzed and the optimal idle state is obtained.

TM-RF: Aging-Aware Power-Efficient Register File Design for Modern Microprocessors

Modern microprocessors employ register files (RFs) for performance enhancement and achieving instruction level parallelism simultaneously. However, RF incurs large power consumption owing to the highly frequent access. Meanwhile, as technology scales, bias temperature instability has become a major reliability concern for RF designers. This paper presents an aging-aware trimodal register file (TM-RF) design to enhance the power efficiency. As instructions pass through the pipeline, TM-RF places the bit-cells in different modes based on the register activity, thereby achieving significant power reduction. To meet design constraints of different applications, we present four schemes to implement the proposed design, providing design flexibility. Additionally, with device selection and worst case sizing methodology, we mitigate aging-effect-induced RF reliability degradation. Simulation results on SPEC 2000 benchmarks demonstrate that TM-RF achieves up to 81.4% power savings and 17% reliability improvement on average, with minimal impact on performance.

Application-driven power efficient ALU design methodology for modern microprocessors

In this paper, we propose an application-driven ALU design methodology to achieve high level of power efficiency for modern microprocessors. We introduce a PN selection algorithm (PNSA) which enables designers to select power efficient dynamic modules for different applications, based on the detailed analysis of dynamic circuits. Experimental results on ISCAS85 and 74X-Series benchmark circuits show that the power consumption of 8-bit ALU based on this approach can be reduced by 54%-60% for different frequency levels as compared to the conventional dynamic ALU design, demonstrating the effectiveness of the proposed method on application-driven custom ALU design.