Lihua Dai

Total dose radiation induced changes of the floating body effects in the partially depleted SOI NMOS with ultrathin gate oxide

In this paper, the impacts of total dose radiation on the lowfrequency noise and gate induced floating body effects (GIFBEs) for the 130 nm partially depleted silicon-on-insulator N-type metal-oxide semiconductors transistor with an ultrathin gate oxide have been investigated. It is shown that the second transconductance gm peak becomes smaller after irradiation when the Lorentzian-like excess noise is more pronounced. The traps induced by irradiation at shallow trench isolation/body and buriedoxide/body interface can act as the recombination centers to increase the source-body diode current, which results in the changes in the excess noise and GIFBEs.

Metastable Electron Traps in Modified Silicon-on-Insulator Wafer*

We perform the total ionizing radiation and electrical stress experiments to investigate the electrical characteristics of the modified silicon-on-insulator (SOI) wafers under different Si ion implantation conditions. It is confirmed that Si implantation into the buried oxide can create deep electron traps with large capture cross section to effectively improve the antiradiation capability of the SOI device. It is first proposed that the metastable electron traps accompanied with Si implantation can be avoided by adjusting the peak location of the Si implantation reasonably.

Enhanced radiation-induced narrow channel effects in 0.13-

Total ionizing dose responses of different transistor geometries after being irradiated by 60Co γ-rays, in 0.13- partially-depleted silicon-on-insulator (PD SOI) technology are investigated. The negative threshold voltage shift in an n-type metal-oxide semiconductor field effect transistor (nMOSFET) is inversely proportional to the channel width due to radiation-induced charges trapped in trench oxide, which is called the radiation-induced narrow channel effect (RINCE). The analysis based on a charge sharing model and three-dimensional technology computer aided design (TCAD) simulations demonstrate that phenomenon. The radiation-induced leakage currents under different drain biases are also discussed in detail.

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Silicon-on-insulator (SOI) devices are sensitive to the total ionizing dose effect due to the existence of buried oxide. In this paper, an extra single-step Si ion implantation into buried oxide layer prior to the normal complementary metal–oxide–semiconductor transistor (CMOS) process is used to harden the SOI wafer. The top-Si quality of the hardened SOI wafer is confirmed to be good enough for device manufacturing through various characterization methods. The radiation experiments show that the total ionizing dose tolerance of the Si implanted SOI device is improved significantly. The metastable electron traps introduced by Si implantation is also investigated by electrical stress. The results show that these traps are very instable, and electrons will tunnel into or out of the metastable electron traps quickly after hot-electron-injection or hot-hole-injection.

PDSOI nMOSFETs with shallow trench isolation

Single-event upsets are studied in digital storage cells in 130nm CMOS bulk Si and PDSOI technologies. The sensitivity of SEU to different technologies and hardening approaches is explored by using heavy-ion radiation experiments. Error numbers in D flip-flop chains are used to determine the impact of various cell designs and PDSOI hardening technique on upset sensitivity. Various flip-flops are designed and connected as shift-register chains, and the error numbers induced by irradiation are recorded to examine the effectiveness of the PDSOI technology. It was found that PDSOI technology has better performance in terms of upset robustness versus bulk Si at the 130nm technology node. The same design structure implemented in PDSOI technology has higher SEU threshold LET and much lower saturation cross section due to its full dielectric isolation structure which does not allow the charge generated in the substrate to be collected by the electrically active junctions in the thin top region of the device and reduces the sensitive volume of p-n junctions in the transistor. As shown in the experiment result, NRH_SOI (not radiation hardening SOI) saves about 25% area while having much lower SER versus DICE_Si, which means PDSOI still has obvious advantage at reducing SEU rate, even though its necessary body contact has to consume certain extra area.

Research on the radiation hardened SOI devices with single-step Si ion implantation

We have investigated the direct-current characteristics of the 130-nm partially depleted SOI NMOSFETs fabricated on modified wafer with silicon ion implantation and control wafer before and after total dose radiation. Due to the deep electron traps in buried oxide, the back gate threshold voltage of the modified SOI device increases when hot electrons are injected into the buried oxide. Moreover, due to this electrons injection process, the Top-Si/buried-oxide interface produces donor-like electron traps, which results in a kink effect in I-V characteristic curve and double gm peak behavior in back gate transistor. By TCAD simulation, we have demonstrated that the deformation of the I-V curve depends on the density of the interface trap on the premise of double gm peak generation. It was speculated that hot electrons injection could produce Si-O weak bond and weak interaction with the peculiar bonding parameter at the Top-Si/BOX interface. Finally, the radiation results show that silicon ion implantation can effectively enhance the radiation hardness performance of the SOI material.