Linfei Guo

A 101 dB PSRR, 0.0027% THD + N and 94% Power-Efficiency Filterless Class D Amplifier

Present-day smartphones and tablets demand high audio fidelity (e.g., total harmonic distortion + noise, THD + N ≪ 0.01%), and high noise immunity (e.g., power supply rejection ratio, PSRR ≫ 80 dB) to allow high integration in an SoC. The design of conventional closed-loop pulse width modulation (PWM) Class-D amplifiers (CDAs) typically involves undesirable trade-offs between fidelity (qualified by THD + N), PSRR and switching frequency. In this paper, we propose a fully integrated CMOS CDA that embodies a novel input-modulated carrier generator and a novel phase-error-free PWM modulator, collectively allowing the employment of high loop-gain to achieve high PSRR, yet without compromising linearity/dynamic-range or resorting to high switching frequency. The prototype CDA, realized in 65 nm CMOS, achieves a THD + N of 0.0027% and a power efficiency of 94% when delivering 500 mW to an 8 Ω load from VDD = 3.6 V. The PSRR of the prototype CDA is very high, -101 dB @217 Hz and 90 dB @1 kHz, arguably the highest to-date. Furthermore, the switching frequency of the prototype CDA varies from ~320 to 420 kHz, potentially reducing the EMI due to spread-spectrum. In addition, the prototype CDA is versatile with a large operating-voltage range, with V ranging from rechargeable 1.2 V single battery to standard 3.6 V smart-device supply voltages.

Intermodulation Distortions of Bang–Bang Control Class D Amplifiers

Audio Class D amplifiers (CDAs) based on bang-bang architecture are arguably the most power efficient architecture of all CDAs reported to-date due to their sheer hardware simplicity. At this juncture, the intermodulation distortion (IMD), an imperative measure that defines fidelity, remains unreported for bang-bang CDAs. In this paper, we investigate the mechanisms of and circuit parameters affecting the IMD of bang-bang CDAs. An interesting phenomenon is that the even-order IMD which is usually negligible/unreported in other CDAs and linear amplifiers may be higher than odd-order IMD therein. We derive analytical expressions for the IMD of the ideal and practical bang-bang CDAs, and the derived expressions are verified against HSPICE simulations and on the basis of measurements on a physical bang-bang CDA. These derived analytical expressions are useful as they provide valuable insights to the design of bang-bang CDAs and how parameters can be tradedoff to improve the IMD.

A micropower comparator for high power-efficiency hearing aid class D amplifiers

Class D amplifiers are routinely employed in power-critical hearing aids for their high power-efficiencies, typically ~90% at high modulation indexes. Nevertheless, at the nominal operation condition where the modulation index M=0.1, the power-efficiency is typically 32%. In this paper, we show that the comparator embodied in the over-current protection circuit of the Class D output stage is dominant at M=0.1. We propose the design of a novel comparator (with performance parameters comparable with conventional comparators) featuring ~40% lower power dissipation. This improved lower power dissipation translates to a worthwhile 12% improvement in the power-efficiency of the Class D amplifier output stage. The proposed design herein is verified by computer simulations.

A novel low-power high-efficiency 3-state filterless bang-bang class D amplifier

Of the reported modulation techniques for Class D amplifiers (CDAs), CDAs based on Bang-Bang control modulation are arguably the most advantageous in terms of power-efficiency for low-power power-critical applications. To date, only single-ended and 2-state Bang-Bang control CDAs have been reported, and are hence disadvantageous because they require a bulky and costly output lowpass filter. In this paper, we propose the first-ever 3-state Bang-Bang control filterless CDA applicable to regular-power and ultra-low-power applications. Compared to other filterless 3-state CDAs, the proposed filterless 3-state Bang-Bang control CDA features the simplest hardware and the highest power-efficiency, but with somewhat compromised fidelity. Nevertheless, the fidelity thereto is sufficient for typical ultra-low-power applications such as low-to-mid performance wearable devices.

An Ultralow-Power Overcurrent Protection Circuit for Micropower Class D Amplifiers

Although class D amplifiers (CDAs) are highly advantageous over their linear amplifier counterparts in terms of power efficiency, their power efficiency remains undesirably low at nominal operation conditions where the output power is ~26 dB lower than its peak output power (due to the large crest factor of the audio/speech signal and headroom for adjustment). This is particularly the case for power-critical micropower applications such as hearing instruments. At nominal conditions, we find that the overcurrent protection circuit (for the output stage) is unexpectedly the most power-dissipative block in micropower CDAs. In this brief, we propose a novel ultralow-power overcurrent protection circuit, which features 67% lower power dissipation compared to conventional overcurrent protection circuit without compromising the IC area. To further verify the advantages of the proposed overcurrent protection circuit, an ultralow-power bang-bang CDA is designed. We show that, by employing the proposed overcurrent protection circuit, the power efficiency of the bang-bang CDA is significantly improved from 10.5% to 23.7% for a 64-Ω load and from 1.8% to 4.7% for a 400-Ω load.

An investigation into the effect of carrier generators on power supply noise in PWM Class D amplifiers

Class D amplifiers are ubiquitous as audio amplifiers due to their significantly higher power-efficiency compared to their linear counterparts (such as Class AB) due to the digital-like switching mode operation of the Class D output stage. However, one drawback of Class D amplifiers is the susceptibility to supply noise, qualified and quantified by Power Supply Rejection Ratio (PSRR) and Power Supply Induced Intermodulation Distortion (PS-IMD). In this paper, PSRR and PS-IMD of Single-ended, 2-state bridge-tied load (BTL) and 3-state BTL Class D amplifiers based on various carrier generators are investigated and compared. We show that the design of the carrier generator is critical and should be designed according to the structure of the Class D amplifier - we show in this paper that the same Carrier Generator may result in a high >70dB PSRR in a 3-state BTL Class D amplifier but an unacceptable 1dB PSRR in a 2-state BTL Class D amplifier. The investigation and comparison provide Class D amplifier designers useful insight on design and optimization of PSRR and PS-IMD.

Effect of carrier topologies on PSRR and PS-IMD of open-loop Class D amplifiers for hearing aids

Open-Loop Pulse Width Modulation (PWM) Class D amplifiers are attractive for power critical applications including hearing aids due to their simple hardware and high power-efficiency. Nevertheless, a drawback of open-loop Class D amplifiers is their susceptibility to supply noise, quantified by power supply rejection ratio (PSRR) and power supply induced intermodulation distortion (PS-IMD). In this paper, PSRR and PS-IMD of a commonly-used carrier generation method are investigated and compared against other common carrier generation methods. The analyses are verified by means of HSPICE simulations. The analyses and comparisons provide designers useful insight to the design of power critical Class D amplifiers.