Joseph Sylvester Chang

A parametric formulation of the generalized spectral subtraction method

In this paper, two short-time spectral amplitude estimators of the speech signal are derived based on a parametric formulation of the original generalized spectral subtraction method. The objective is to improve the noise suppression performance of the original method while maintaining its computational simplicity. The proposed parametric formulation describes the original method and several of its modifications. Based on the formulation, the speech spectral amplitude estimator is derived and optimized by minimizing the mean-square error (MSE) of the speech spectrum. With a constraint imposed on the parameters inherent in the formulation, a second estimator is also derived and optimized. The two estimators are different from those derived in most modified spectral subtraction methods, which are predominantly nonstatistical. When tested under stationary white Gaussian noise and semistationary Jeep noise, they showed improved noise suppression results.

Analysis and design of power efficient class D amplifier output stages

A Class D amplifier comprises a pulse width modulator and an output stage. In this paper we analyze the power dissipation mechanisms and derive the overall power efficiency of the output stage realized using the finger and waffle layouts. We compare the relative merits of these layouts; we propose two design methodologies to determine the aspect ratios of the transistors in the output stage for optimum power efficiency (optimum for a given fabrication process, supply voltage and load resistance): (1) optimization to a single modulation index point and (2) optimization to a range of modulation indexes. For the design of an output stage with optimum power efficiency (and small IC area), we recommend optimization to a range of modulation indexes and a layout realized by the waffle structure. The theoretical analysis and derivations are verified on the basis of computer simulations and measurements on fabricated prototype ICs.

A micropower low-distortion digital class-D amplifier based on an algorithmic pulsewidth modulator

A digital Class-D amplifier comprises a pulsewidth modulator (PWM) and an output stage. In this paper, we simplify the time-domain expression for the algorithmic PWM linear interpolation (LI) sampling process and analytically derive its double Fourier series expression. By means of our derivation, we show that the nonlinearities of the LI process are very low, especially given its modest computation complexity and low sampling frequency. In particular, the total-harmonic distortion (THD) /spl ap/0.02% and foldback distortion is -98.4 dB (averaged from modulation indexes M=0.1 to 0.9) for the 4-kHz voiceband bandwidth @1-kHz input, 48-kHz sampling. We also describe a simple hardware for realizing the LI process. We propose a frequency doubler (with small overheads) for the pulse generator for the PWM, thereby reducing the counter clock rate by 2, leading to a substantial /spl sim/47% power dissipation reduction for the Class-D amplifier. By means of computer simulations and on the basis of experimental measurements, we verify our double Fourier series derivation and show the attractive attributes of a Class-D amplifier embodying our simplified LI sampling expression and reduced clock rate pulse generator. We show that our Class-D amplifier design is micropower (/spl sim/60 /spl mu/W @1.1 V and 48-kHz sampling rate, and THD /spl ap/0.03%) and is suitable for practical power-critical portable audio devices, including digital hearing aids.

A micropower low-distortion digital pulsewidth modulator for a digital class D amplifier

We describe the design of a micropower digital pulsewidth modulator (PWM) for a hearing instrument class D amplifier. The PWM embodies a novel delta-compensation (/spl delta/C) sampling process and a novel pulse generator. The /spl delta/C process is sampled at the same low rate as reported algorithmic sampling processes and it features a similar low total harmonic distortion (THD). Its arithmetic computation is however, substantially simplified. We analytically derive the double Fourier series expression for the /spl delta/C process and show that the THD is low. The pulse generator is based on a hybrid 9-b counter 3-b tapped-delay-line. We investigate the compromise between the different design parameters that affect its power dissipation and THD. The complete proposed PWM features a simple circuit implementation (small IC area), micropower low voltage operation (/spl sim/22.1 /spl mu/W at 1.1 V), low sampling rate (48 kHz) and low harmonic distortion (/spl sim/0.2%), thereby rendering it suitable for a practical digital hearing instrument. We verify our design by means of computer simulations and on the basis of experimental measurements.

A micropower low-voltage multiplier with reduced spurious switching

We describe a micropower 16times16-bit multiplier (18.8 muW/MHz @1.1 V) for low-voltage power-critical low speed (les5 MHz) applications including hearing aids. We achieve the micropower operation by substantially reducing (by ~62% and ~79% compared to conventional 16times16-bit and 32times32-bit designs respectively) the spurious switching in the Adder Block in the multiplier. The approach taken is to use latches to synchronize the inputs to the adders in the Adder Block in a predetermined chronological sequence. The hardware penalty of the latches is small because the latches are integrated (as opposed to external latches) into the adder, termed the latch adder (LA). By means of the LAs and timing, the number of switchings (spurious and that for computation) is reduced from ~5.6 and ~10 per adder in the adder block in conventional 16times16-bit and 32times32-bit designs respectively to ~2 in our designs. Based on simulations and measurements on prototype ICs (0.35 mum three metal dual poly CMOS process), we show that our 16times16-bit design dissipates ~32% less power, is ~20% slower but has ~20% better energy-delay-product (EDP) than conventional 16times16-bit multipliers. Our 32times32-bit design is estimated to dissipate ~53% less power, ~29% slower but is ~39% better EDP than the conventional general multiplier

An investigation into the parameters affecting total harmonic distortion in low-voltage low-power Class-D amplifiers

We investigate the influence of two important practical design parameters on total harmonic distortion (THD) for the design of low-voltage (0.9-1.4 V) low-power analog Class-D amplifiers: the linearity of the carrier waveform and the impedance of the output stage. We show that the carrier nonlinearity results in THD and propose a novel mathematical analysis method to model the nonlinearity. We recommend a range of the parameter that describes the carrier nonlinearity and that results in a good compromise to the dynamic range of the pulsewidth modulator of the Class-D amplifier. We show that the impedance of the output stage has little effect on THD. We verify our analyses by means of MATLAB and HSPICE computer simulations, and on the basis of practical measurements.

A 16-Channel Low-Power Nonuniform Spaced Filter Bank Core for Digital Hearing Aids

We describe a 16-channel critical-like spaced, high stopband attenuation (ges60 dB, 109thtimes16-order), micropower (247.5 muW@1.1 V, 0.96 MHz), small integrated circuit (IC) area (1.62 mm2@0.35-mum CMOS) finite impulse response filter bank core for power-critical hearing aids. We achieve the low-power and small IC area attributes by our proposed common pre-computational unit to generate a set of pre-calculated intermediate values that is shared by all 16 channels. We also take advantage of the consecutive zeros in the coefficients of the filter channels, allowing the multiplexers therein to be simplified. We show that our design is very competitive compared to reported designs, and with the advantages of higher stopband attenuation and linear phase frequency response. Compared to a design using the usual approach, our design features 47% lower power dissipation and 37% smaller IC area

Energy-Efficient Synchronous-Logic and Asynchronous-Logic FFT/IFFT Processors

Two 128-point 16-bit radix-2 FFT/IFFT processors based on synchronous-logic (sync) and asynchronous-logic (async) for low voltage (1.1-1.4 V) energy-critical low-speed hearing aids are described. The two processors herein are designed with the same function and similar architecture, and the emphasis is energy efficacy. The async approach, on average, features ~37% lower energy per FFT/IFFT computation than the sync approach but with ~10% larger IC area penalty and an inconsequential 1.4 times worse delay; the async design can be designed to be 0.24 times faster and with largely the same energy dissipation if the matched delay elements and the latch controllers therein are better optimized. In this low-speed application, the lower energy feature of the async design is not attributed to the absence of the clock infrastructure but instead due to the adoption of established and proposed async circuit designs, resulting in reduced redundant operations and reduced spurious/glitch switching, and to the use of latches. The prototype async FFT/IFFT processor (in a 0.35-mum CMOS process) can be operated at 1.0 V and dissipates 93 nJ.

Modeling and Technique to Improve PSRR and PS-IMD in Analog PWM Class-D Amplifiers

Although power-supply noise, qualified by power- supply rejection ratio (PSRR), has been recognized as a potential drawback of Class-D amplifiers (CDAs) compared to linear amplifiers, the mechanisms of PSRR for CDAs are not well established. It is also not well recognized that the power-supply noise can intermodulate with the input signal, manifesting into power-supply induced intermodulation distortion (PS-IMD), and that the PS-IMD can be significantly larger than the output distortion component at supply noise frequency. Furthermore, techniques to improve PSRR and PS-IMD are largely unreported in literature. In this brief, by means of a linear model, the PSRR and PS-IMD of single-feedback and double-feedback CDAs are analyzed and analytical expressions derived. A simple method is proposed to improve PSRR and PS-IMD with very low hardware overheads, and the improvement is ~ 26 dB. Analytical expressions for PSRR and PS-IMD of the improved design are derived and the pertinent parameters thereof are investigated. The model and analyses provide practical insight to the mechanisms of PSRR and PS-IMD, and how various parameters may be varied to meet a given specification.

THD of Closed-Loop Analog PWM Class-D Amplifiers

This paper presents an analytical modeling of the mechanisms of total harmonic distortion (THD) of second-order based single-feedback and double-feedback class-D amplifiers (CDAs). We show that the overall THD in these closed-loop CDAs comprises the THD of their open-loop counterparts reduced by the Loop Gain+1 and the THD due to the combined phase and duty cycle error that is due to feedback, hence unique to closed-loop CDAs. We show that the latter THD can be large and is the dominant THD at high input frequencies ( > 3 kHz), and that the mechanisms therein are the phase and duty cycle errors. By means of double Fourier series analysis, analytical expressions for the harmonic components and thereafter a THD expression for closed-loop CDAs are derived. The derived expressions depict the parameters that affect THD, and are insightful to designers to optimize/vary pertinent parameters to reduce THD. The derived THD expression is verified against HSPICE and on the basis of measurements on a prototype CDA IC and other CDAs realized discretely.