Lingli Xia

0.56 V, –20 dBm RF-Powered, Multi-Node Wireless Body Area Network System-on-a-Chip With Harvesting-Efficiency Tracking Loop

A battery-less, multi-node wireless body area network (WBAN) system-on-a-chip (SoC) is demonstrated. An efficiency tracking loop is proposed that adjusts the rectifiers threshold voltage to maximize the wireless harvesting operation, resulting in a minimum RF sensitivity better than -20 dBm at 904.5 MHz. Each SoC node is injection-locked and time-synchronized with the broadcasted RF basestation power (up to a sensitivity of -33 dBm) using an injection-locked frequency divider (ILFD). Hence, every sensor node is phase-locked with the basestation and all nodes can wirelessly transmit TDMA sensor data concurrently. Designed in a 65 nm-CMOS process, the fabricated sensor SoC contains the energy harvesting rectifier and bandgap, duty-cycled ADC, digital logic, as well as the multi-node wireless clock synchronization and MICS-band transmitter. For a broadcasted basestation power of 20 dBm (30 dBm), experimental measurements verify correct powering, sensor reading, and wireless data transfer for a distance of 3 m (9 m). The entire biomedical system application is verified by reception of room and abdominal temperature monitoring.

A Near-Threshold, 0.16 nJ/b OOK-Transmitter With 0.18 nJ/b Noise-Cancelling Super-Regenerative Receiver for the Medical Implant Communications Service

A 0.16 nJ/b MICS transmitter and 0.18 nJ/b super-regenerative receiver are demonstrated, where each is specifically designed to operate in the near-threshold region. The low-VDD transmitter utilizes a sub-harmonic injection-locked ring oscillator, edge combiner for frequency multiplication, and class-C power amplifier. The low-VDD receiver introduces a replica super-regenerative receiver as a method to reject common-mode noise sources, such as supply/substrate coupling, thereby reducing undesired self-oscillations and improving BER. Designed in a 90-nm CMOS process, the test-chip measurements show a sensitivity of -80 dBm at 500 kb/s and -65 dBm at 1 Mb/s, respectively, at a BER less than 10-3, with 340 μW total power.

Experimental characterization of a UWB channel for body area networks

Ultrawideband (UWB) communication is a promising technology for wireless body area networks (BANs), especially for applications that require transmission of both low and high data rates with excellent energy efficiency. Therefore, understanding the unique UWB channel propagation characteristics around the human body is critical for a successful wireless system, especially for insuring the reliability of important vital sign data. Previous work has focused only on on-body channels, where both TX and RX antennas are located on the human body. In this paper, a 3–5 GHz UWB channel is measured and analyzed for human body wireless communications. Beyond the conventional on-body channel model, line-of-sight (LOS) and non-line-of-sight (NLOS) channel models are obtained using a TX antenna placed at various locations of the human body while the RX antenna is placed away from the human body. Measurement results indicate that the human body does not significantly degrade the impedance of a monopole omnidirectional antenna. The measured path loss and multipath analysis suggest that a LOS UWB channel is excellent for low-power, high-data-rate transmission, while NLOS and on-body channels need to be reconfigured to operate at a lower data rate due to high path loss.

A near-threshold, multi-node, wireless body area sensor network powered by RF energy harvesting

A wirelessly-powered, near-threshold, body area network SoC supporting synchronized multi-node TDMA operation is demonstrated in 65nm CMOS. A global clock source sent from a base-station wirelessly broadcasts at 434.16MHz to all sensor nodes, where each individual BAN sensor is phase-locked to the base-station clock using a super-harmonic injection-locked frequency divider. Each near-threshold SoC harvests energy from and phase locks to this broadcasted 434.16MHz waveform, eliminating the need for a battery. A Near-VT MICS-band OOK transmitter sends the synchronized local sensor data back to the base-station in its pre-defined TDMA slot. For an energy-harvested local VDD=0.56V, measurements demonstrate full functionality over 1.4m between the base-station and four worn sensors, including two that are NLOS. The sensitivity of the RF energy harvesting and the wireless clock synchronization are measured at -8dBm and -35dBm, respectively. ECG Lead-II/Lead-III waveforms are experimentally captured, demonstrating the end-to-end system application.

Sub-2-ps, Static Phase Error Calibration Technique Incorporating Measurement Uncertainty Cancellation for Multi-Gigahertz Time-Interleaved T/H Circuits

A foreground digital calibration method is presented that calibrates the timing offsets between the multiple T/H (track/hold) circuits of time-interleaved analog-to-digital converters and multi-phase serial links. Two quantizer-based phase detectors sample the outputs of adjacent track/hold circuits, detecting any phase offsets arising from process mismatches in both the timing verniers and the T/H switches, and store the resulting digital decisions in histogram counters. Measurement inaccuracies resulting from quantizer offset are averaged away statistically by a round-robin rotation of the dual samplers, compensating for comparator imprecision. Built in a 90-nm CMOS process, the proposed calibration technique, after three iterations of both the phase measurement and subsequent timing vernier adjustment, reduces the static phase offset of each channel to less than ±0.5 ps in an 8-channel, 8 GS/s time-interleaved system. Further measurements using a T/H circuit as a down-conversion mixer confirm a residual phase error of less than ±2 ps.

Innovative approach to server performance and power monitoring in data centers using wireless sensors (invited paper)

Data Centers face considerable challenges in seamless propagation of telemetry data and executing control functions for performing various management functions. These functions are related to power capping, cooling, reliability, predictability, survivability, and adaptability control. In a conventional approach, distributed sense-data in a server node is collected through wired management interconnects and LAN. We present an alternative approach for this unique data center environment using wireless sensor network to improve data-collection efficiency and real-time delivery. We survey 2-tier sense data collection methodology using narrow-channel wireless interconnects for server management and RACK-level wireless sensor network for data center management.

Design challenges for ultra-wideband wireless communications within a computer chassis

Conventional metal wiring is becoming an inevitable difficulty for a computing platform. This paper presents an Ultrawideband (UWB) wireless interconnection solution. The channel characteristics within a computer chassis is analyzed, including the path loss, multipath reflections and electromagnetic interferences (EMI). To address the above problems, an IR-UWB transceiver is proposed with equalization in transmitter to relax the multipath reflections and pulse injection-locking for receiver clock recovery and synchronization. The transceiver achieved a significant power saving for high data rate (up to 500Mbps) demodulation.

Ultra Wideband RF Transceiver Design in CMOS Technology

UWB (Ultra-Wideband) is one of the WPAN (Wireless Personal Area Network) Technologies; its main applications include imaging systems, vehicular radar systems and communications and measurement systems. Ever since the FCC released unlicensed spectrum of 3.1-10.6 GHz for UWB application in 2002, UWB has received significant interest from both industry and academia. Comparing with traditional narrowband WPANs, (e.g. Bluetooth, Zigbee, etc.), the most significant characteristics of UWB are ultra-wide bandwidth (7.5 GHz) and low emitted spectrum density (-41.3 dBm/MHz). According to Shannon-Hartley theorem (Wikipedia, 2010), through an AWGN (Additive White Gaussian Noise) channel, the maximum rate of clean (or arbitrarily low bit error rate) data is limited to

Sinusoidal Clock Sampling for Multigigahertz ADCs

Current multigigahertz ADC performance is limited by the sampling clock timing jitter. This paper describes the effects of clock transition time on the spurious-free dynamic range (SFDR) of a CMOS T/H circuit. A signal-dependent nonlinearity model is first introduced that provides insight on the effect of finite clock transition time, and presents the use of sinusoidal signal as the sampling clock to improve SFDR. Whereas a square-wave clock exhibits a shorter transition time but more jitter susceptibility, sinusoidal clocking provides a longer transition time but a lower jitter spectrum. To verify this concept, an 8 GS/s, 4b flash ADC with a sinusoidal clock is designed and experimentally measured, achieving a figure-of-merit of 0.86 pJ/conv-step based upon effective resolution bandwidth (ERBW), and 0.2 pJ/conv-step based upon sampling rate.