Linlin Zhao

A study of 65nm BEOL trench etch issues

65 nm BEOL trench etch is apt to suffer the marginal PR issue. It is a big challenge for trench etch process to simultaneously satisfy the requirements for both metal resistance (Rs) and breakdown Voltage (VBD). The copper surface condition of via bottom is a big concern of trench etch process as well. In this paper, we present several electrical parameter issues that occurred at 65 nm trench etch process such as Rs, via resistance (Rc) and VBD. The feasible solutions and related etching mechanisms are also addressed for the above issues from the point view of the improvement of line-edge roughness (LER), within wafer AEI CDU (critical dimension uniformity) and interface conditions of via-bottom.

Yield Enhancement with Optimized Offset Spacer Etch for 65nm Logic Low-leakage Process

This paper presents an effective way to reduce the degradation of the Ring-OSC speed with optimized offset spacer etch, improvement of the within-wafer uniformity of the offset spacer width and the reduction of its profile deviation. We have developed the lower offset spacer etch rate scheme for better control of plasma uniformity in order to achieve the above two targets. Compared with the 3Sigma of 1.3nm offset spacer width uniformity and 1.8nm profile deviation of conventional dielectric etcher with high etch rate, this low etch rate process has delivered the 3sigma of 0.5nm for the offset spacer width uniformity and 0.7nm offset spacer profile deviation. The corresponding Ring-OSC loss has been completely eliminated and the wafer-level yield is enhanced by 40%.