Linyong Pang

Validation of inverse lithography technology (ILT) and its adaptive SRAF at advanced technology nodes

In this paper, an overview of Inverse Lithography Technology (ILT) based on Level Set Methods (LSM) is provided. Applications of ILT in the advanced lithography process are then shown for several different devices, including DRAM, SRAM, FLASH, random logic, and imaging devices. ILT is used to correct the main patterns, as well as automatically insert SRAFs using model-based mathematical methods. The process of SRAF generation in ILT is unified with the process of inversion. With the help of ILT, SRAFs can be inserted where physically needed, independent of source parameters or target patterns. Results that demonstrate the adaptive nature of ILT SRAF insertion capability are presented. Wafer verification results were collected by multiple advanced semiconductor manufacturing companies at advanced technology nodes, including 45nm and 32nm nodes, and compared with their current OPC solution. Final wafer results presented here demonstrate that ILT improves pattern fidelity, enlarges process window, and provides remarkable control for line-end shortening.

Compensation methods using a new model for buried defects in extreme ultraviolet lithography masks

A new method for predicting the reflection from an extreme ultraviolet (EUV) multilayer is described which when implemented into the new Defect Printability Simulator (DPS) can calculate the image produced by an EUV mask with a buried defect several orders of magnitude faster than the finite difference time domain (FDTD). A new buried defect compensation method is also demonstrated to correct the in focus image of a line space pattern containing a buried defect. The new multilayer model accounts for the disruption of the magnitude and phase of the reflected field from an EUV multilayer defect. It does this by sampling the multilayer on a non-uniform grid and calculating the analytic complex local reflection coefficient at each point. After this step, the effect of the optical path difference due to the surface defect profile is added to the total reflected field to accurately predict the reflected magnitude and phase at all points on the multilayer surface. The accuracy of the new multilayer model and the full DPS simulator is verified by comparisons to FDTD simulations. The largest difference between the two methods was 0.8nm for predicting the CD change due to a buried defect through focus. This small difference is within the margin of error for FDTD simulations of EUV multilayers. The runtime of DPS is compared to extrapolated FDTD runtimes for many simulation domain sizes and DPS is 4-5 orders of magnitude faster for all cases. For example, DPS can calculate the reflected image from a 1μm x 1μm mask area in less than 30 seconds on a single processor. FDTD would take a month on four processors. The new compensation strategy demonstrated in this work is able to remove all CD error in the simulated image due to a buried defect in a 22nm dense line space pattern. The method is iterative and a full DPS simulation is run for every iteration. After each simulation, the absorber pattern is adjusted based on the difference of the thresholded target image and thresholded defective image. This method is very simple and does not attempt to compensate for the defect through focus, but it does demonstrate the usefulness of a fast simulator for compensation.

Exploration of complex metal 2D design rules using inverse lithography

As design rule (DR) scaling continues to push lithographic imaging to higher numerical aperture (NA) and smaller k1 factor, extensive use of resolution enhancement techniques becomes a general practice. Use of these techniques not only adds considerable complexity to the design rules themselves, but also can lead to undesired and/or unanticipated problematic imaging effects known as hotspots. This is particularly common for metal layers in interconnect patterning due to the many complex random and bidirectional (2D) patterns present in typical layout. In such situations, the validation of DR becomes challenging, and the ability to analyze large numbers of 2D layouts is paramount in generating a DR set that encodes all lithographic constraints to avoid hotspot formation. Process window (PW) and mask error enhancement factor (MEEF) are the two most important lithographic constraints in defining design rules. Traditionally, characterization of PW and MEEF by simulation has been carried out using discrete cut planes. For a complex 2D pattern or a large 2D layout, this approach is intractable, as the most likely location of the PW or MEEF hotspots often cannot be predicted empirically, and the use of large numbers of cut planes to ensure all hotspots are detected leads to excessive simulation time. In this paper, we present a novel approach to analyzing fullfield PW and MEEF using the inverse lithography technology (ILT) technique, [1] in the context of restrictive design rule development for the 32nm node. Using this technique, PW and MEEF are evaluated on every pixel within a design, thereby addressing the limitations of cut-plane approach while providing a complete view of lithographic performance. In addition, we have developed an analysis technique using color bitmaps that greatly facilitates visualization of PW and MEEF hotspots anywhere in the design and at an arbitrary level of resolution. We have employed the ILT technique to explore metal patterning options and their impact on 2D design rules. We show the utility of this technique to quickly screen specific rule and process choices-including illumination condition and process bias-using large numbers of parameterized structures. We further demonstrate how this technique can be used to ascertain the full 2D impact of these choices using carefully constructed regression suites based on standard random logic cells. The results of this study demonstrate how this simulation approach can greatly improve the accuracy and quality of 2D rules, while simultaneously accelerating learning cycles in the design phase.

Computational metrology and inspection (CMI) in mask inspection, metrology, review, and repair

Abstract Mask manufacturers will be impacted by two significant technology requirements at 22 nm and below: the first is the more extensive use of resolution enhancement technologies (RET), such as aggressive optical proximity correction (OPC), inverse lithography technology (ILT), and source mask optimization (SMO); the second is the extreme ultraviolet (EUV) technology. Both will create difficulties for mask inspection, defect disposition, metrology, review, and repair. For example, the use of ILT and SMO significantly increases mask complexity, making mask defect disposition more challenging than ever. The EUV actinic inspection and AIMS™ will not be available for at least a few years, which make the EUV defect inspection and disposition more difficult, particularly regarding multilayer defects. Computational metrology and inspection (CMI), which has broad applications in mask inspection, metrology, review, and repair, has become essential to fill this technology gap. In this paper, several such CMI applications are presented and discussed.

Source-mask optimization (SMO): from theory to practice

Source Mask Optimization techniques are gaining increasing attention as RET computational lithography techniques in sub-32nm design nodes. However, practical use of this technique requires careful considerations in the use of the obtained pixilated or composite source and mask solutions, along with accurate modeling of mask, resist, and optics, including scanner scalar and vector aberrations as part of the optimization process. We present here a theory-to-practice case of applying ILT-based SMO on 22nm design patterns.

Optimization from design rules, source and mask, to full chip with a single computational lithography framework: level-set-methods-based inverse lithography technology (ILT)

For semiconductor manufacturers moving toward advanced technology nodes -32nm, 22nm and below - lithography presents a great challenge, because it is fundamentally constrained by basic principles of optical physics. Because no major lithography hardware improvements are expected over the next couple years, Computational Lithography has been recognized by the industry as the key technology needed to drive lithographic performance. This implies not only simultaneous co-optimization of all the lithographic enhancement tricks that have been learned over the years, but that they also be pushed to the limit by powerful computational techniques and systems. In this paper a single computational lithography framework for design, mask, and source co-optimization will be explained in non-mathematical language. A number of memory and logic device results at the 32nm node and below are presented to demonstrate the benefits of Level-Set-Method-based ILT in applications covering design rule optimization, SMO, and full-chip correction.

Evaluation of Inverse Lithography Technology for 55nm-node memory device

Model based OPC has been generally used to correct proximity effects down to ~50 nm critical dimensions at k1 values around 0.3. As design rules shrink and k1 drops below 0.3, however; it is very hard to obtain enough process window and acceptable MEEF (Mask Error Enhancement Factor) with conventional model based OPC. Recently, ILT (Inverse Lithography Technology) has been introduced and has demonstrated wider process windows than conventional OPC. The ILT developed by Luminescent uses level-set methods to find the optimal photo mask layout, which maximizes the process window subject to mask manufacturing constraints. We have evaluated performance of ILT for critical dimensions of 55nm, printed under conditions corresponding to k1 ~ 0.28. Results indicated a larger process window and better pattern fidelity than obtained with other methods. In this paper, we present the optimization procedures, model calibration and evaluation results for 55 nm metal and contact layers and discuss the possibilities and the limitations of this new technology.

Litho/Design Co-Optimization and Area Scaling for the 22-nm Logic Node

We present a comprehensive study of area scaling for 22nm-logicnode routed metal/via layers as a function of route pitch and patterning strategy in both single-exposure (SE) and doublepatterning (DP) regimes. For each candidate route pitch (8856nm), we determine an optimal illumination scheme and develop layout rules for the metal layers. A perturbative area model is used to approximate the impact of the candidate rule set on area scaling. For the most promising SE case, we apply a novel ‘source/design optimization’ technique to further optimize illumination and rules, wherein we extend the source-mask optimization approach (1) by allowing design rules to vary in the analysis. We demonstrate that the optimal area scaling achievable with DP techniques can be vastly superior to SE, and therefore may justify the associated additional cost per wafer.

Evaluation of lithographic benefits of using ILT techniques for 22nm-node

As increasing complexity of design and scaling continue to push lithographic imaging to its k1 limit, lithographers have been developing computational lithography solutions to extend 193nm immersion lithography to the 22nm technology node. In our paper, we investigate the beneficial source or mask solutions with respect to pattern fidelity and process variation (PV) band performances for 1D through pitch patterns, SRAM and Random Logic Standard Cells. The performances of two different computational lithography solutions, idealized un-constrained ILT mask and manhattanized mask rule constrain (MRC) compliant mask, are compared. Additionally performance benefits for process-window aware hybrid assist feature (AF) are gauged against traditional rule-based AF. The results of this study will demonstrate the lithographic performance contribution that can be obtained from these mask optimization techniques in addition to what source optimization can achieve.

Expanding the applications of computational lithography and inspection (CLI) in mask inspection, metrology, review, and repair

Mask manufacturers will be impacted by two significant technology requirements at 22nm and below: The first is more extensive use of resolution enhancement technologies (RET), such as OPC or Inverse Lithography Technology (ILT), and Source Mask Optimization (SMO); the second is EUV technology. Both will create difficulties for mask inspection, defect disposition, metrology, review, and repair. For example, the use of ILT and SMO significantly increases mask complexity, making mask defect disposition more challenging than ever. EUV actinic inspection and AIMSTM will not be available for at least a few years, which makes EUV defect inspection and disposition more difficult, particularly regarding multilayer defects. Computational Lithography and Inspection (CLI), which has broad applications in mask inspection, metrology, review, and repair, has become essential to fill this technology gap. In this paper, several such CLI applications are presented and discussed.