Thuc Dam

Validation of inverse lithography technology (ILT) and its adaptive SRAF at advanced technology nodes

In this paper, an overview of Inverse Lithography Technology (ILT) based on Level Set Methods (LSM) is provided. Applications of ILT in the advanced lithography process are then shown for several different devices, including DRAM, SRAM, FLASH, random logic, and imaging devices. ILT is used to correct the main patterns, as well as automatically insert SRAFs using model-based mathematical methods. The process of SRAF generation in ILT is unified with the process of inversion. With the help of ILT, SRAFs can be inserted where physically needed, independent of source parameters or target patterns. Results that demonstrate the adaptive nature of ILT SRAF insertion capability are presented. Wafer verification results were collected by multiple advanced semiconductor manufacturing companies at advanced technology nodes, including 45nm and 32nm nodes, and compared with their current OPC solution. Final wafer results presented here demonstrate that ILT improves pattern fidelity, enlarges process window, and provides remarkable control for line-end shortening.

Inverse lithography technology (ILT): keep the balance between SRAF and MRC at 45 and 32 nm

In this paper, we present the Luminescents ILT approach that can rapidly solve for the optimal photomask design. We will discuss the latest development of ILT at Luminescent in the areas of sub-resolution assist feature (SRAF) generation and optimization to improve process window, and mask rule compliance (MRC). Results collected internally and from customers demonstrate that ILT is not only an R&D tool, but also a tool quickly maturing for production qualification at advanced technology nodes. By enforcing the proper constraints while optimizing the masks, ILT can improve process windows while maintaining mask costs at a reasonable level.

Source mask optimization (SMO) at full chip scale using inverse lithography technology (ILT) based on level set methods

For semiconductor manufacturers moving toward advanced technology nodes -32nm, 22nm and below - lithography presents a great challenge, because it is fundamentally constrained by basic principles of optical physics. For years, source optimization and mask pattern correction have been conducted as two separate RET steps. For source optimization, the source was optimized based on fixed mask patterns; in other words, OPC and SRAFs were not considered during source optimization. Recently, some new approaches to Source Mask Optimization (SMO) have been introduced for the lithography development stage. The next important step would be the extension of SMO, and in particular the mask optimization in SMO, into full chip. In this paper, a computational framework based on Level Set Method is presented that enables simultaneous source and mask optimization (using Inverse Lithography Technology, or ILT), and can extend the SMO from single clip, to multiple clips, all the way to full chip. Memory and logic device results at the 32nm node and below are presented which demonstrate the benefits of this level-set-method-based SMO and its extendibility to full chip designs.

Source-mask optimization (SMO): from theory to practice

Source Mask Optimization techniques are gaining increasing attention as RET computational lithography techniques in sub-32nm design nodes. However, practical use of this technique requires careful considerations in the use of the obtained pixilated or composite source and mask solutions, along with accurate modeling of mask, resist, and optics, including scanner scalar and vector aberrations as part of the optimization process. We present here a theory-to-practice case of applying ILT-based SMO on 22nm design patterns.

Optimization from design rules, source and mask, to full chip with a single computational lithography framework: level-set-methods-based inverse lithography technology (ILT)

For semiconductor manufacturers moving toward advanced technology nodes -32nm, 22nm and below - lithography presents a great challenge, because it is fundamentally constrained by basic principles of optical physics. Because no major lithography hardware improvements are expected over the next couple years, Computational Lithography has been recognized by the industry as the key technology needed to drive lithographic performance. This implies not only simultaneous co-optimization of all the lithographic enhancement tricks that have been learned over the years, but that they also be pushed to the limit by powerful computational techniques and systems. In this paper a single computational lithography framework for design, mask, and source co-optimization will be explained in non-mathematical language. A number of memory and logic device results at the 32nm node and below are presented to demonstrate the benefits of Level-Set-Method-based ILT in applications covering design rule optimization, SMO, and full-chip correction.

Evaluation of Inverse Lithography Technology for 55nm-node memory device

Model based OPC has been generally used to correct proximity effects down to ~50 nm critical dimensions at k1 values around 0.3. As design rules shrink and k1 drops below 0.3, however; it is very hard to obtain enough process window and acceptable MEEF (Mask Error Enhancement Factor) with conventional model based OPC. Recently, ILT (Inverse Lithography Technology) has been introduced and has demonstrated wider process windows than conventional OPC. The ILT developed by Luminescent uses level-set methods to find the optimal photo mask layout, which maximizes the process window subject to mask manufacturing constraints. We have evaluated performance of ILT for critical dimensions of 55nm, printed under conditions corresponding to k1 ~ 0.28. Results indicated a larger process window and better pattern fidelity than obtained with other methods. In this paper, we present the optimization procedures, model calibration and evaluation results for 55 nm metal and contact layers and discuss the possibilities and the limitations of this new technology.

Exploring the impact of mask making constraints on double patterning design rules

In order to achieve an economical design-to-mask (DTM) development cycle in the low k1 domain, designers, lithographers, and mask makers needed to move away from many sequentially isolated developmental activities onto one collaborative environment managed by a computational lithography platform that integrates their respective ecosystems. 1,2 A successful development cycle used to be achievable by designers providing designs to lithographers, who then provided RET/OPC solutions to realize designs, but once k1 fell below a certain level, the lithographers could not provide solutions to realize some critical designs, which then required feedback to designers for further redesigns requiring further lithographic evaluation cycles. So collaboration and automations between lithographers and designers became necessary to reduce feedback loops and development cycle time. RET and design solutions also were impacted by mask making, and so mask makers feedback on MRC and other constraints needed to be integrated for all three groups to achieve an economical DTM. As many lithographers attempted to print sub-80 nm pitches with 193 nm wavelength, it became necessary to use double patterning to achieve feature resolution. With the effective pitch doubling on each split layer, there could be significant increased design rule freedom for certain complex design situations. Using an integrated computational lithographic platform, one could find design space sweet spots that could further achieve optimal lithographic performance. In this paper, the optimization of design rules (DRD) for double pattern designs (~60 nm pitch) was explored with the mask makers perspective. The experiment to be presented started with a 2x nm design set of clips. Each set of clips underwent size/width/space/pitch variations to generate a design space, and then each design space underwent SMO with an inverse lithography technology (ILT) engine using various mask MRCs and manhattan segmentations. The lithographic results were analyzed with respect to MRC and manhattan segmentation to show their impact on design space and mask solutions.

Litho/Design Co-Optimization and Area Scaling for the 22-nm Logic Node

We present a comprehensive study of area scaling for 22nm-logicnode routed metal/via layers as a function of route pitch and patterning strategy in both single-exposure (SE) and doublepatterning (DP) regimes. For each candidate route pitch (8856nm), we determine an optimal illumination scheme and develop layout rules for the metal layers. A perturbative area model is used to approximate the impact of the candidate rule set on area scaling. For the most promising SE case, we apply a novel ‘source/design optimization’ technique to further optimize illumination and rules, wherein we extend the source-mask optimization approach (1) by allowing design rules to vary in the analysis. We demonstrate that the optimal area scaling achievable with DP techniques can be vastly superior to SE, and therefore may justify the associated additional cost per wafer.

Evaluation of lithographic benefits of using ILT techniques for 22nm-node

As increasing complexity of design and scaling continue to push lithographic imaging to its k1 limit, lithographers have been developing computational lithography solutions to extend 193nm immersion lithography to the 22nm technology node. In our paper, we investigate the beneficial source or mask solutions with respect to pattern fidelity and process variation (PV) band performances for 1D through pitch patterns, SRAM and Random Logic Standard Cells. The performances of two different computational lithography solutions, idealized un-constrained ILT mask and manhattanized mask rule constrain (MRC) compliant mask, are compared. Additionally performance benefits for process-window aware hybrid assist feature (AF) are gauged against traditional rule-based AF. The results of this study will demonstrate the lithographic performance contribution that can be obtained from these mask optimization techniques in addition to what source optimization can achieve.

Comparison of clear-field and dark-field images with optimized masks

Clear-field photo-masks offer significant advantages over dark-field photo-masks for some important classes of target patterns, including small isolated features and dense arrays of contacts. This work compares lithographic performance of clear-field and dark-field images when mask patterns are optimized for respective mask tones. Since the purpose is to study optical behavior, computed images without resist models were compared. In order to explore performance limits, optimized masks were not constrained to limit their complexity. Calculated images were compared for clear-field and dark-field masks, with either opaque or 6% transmission, 180-degree phase-shifted absorbers. In each case, mask patterns were independently optimized to print the targets, which were a set of square and rectangular arrays of contact holes with various dimensions and pitches. The range of the target patterns extended to the limits of ArF resolution with water immersion. Because the intent was to compare inherent optical performance of positive and negative-tone imaging, the study did not use resist models that would combine materials properties or behaviors into the results, but simply applied a constant threshold to calculated intensities to obtain images. Contrast, MEEF, and deviation of images with defocus were the basis of optimizing the mask patterns, and were compared for the four combinations of mask tones and absorbers. Best contrast and MEEF were obtained with bright-field masks that had attenuated, phase-shifting absorbers. The amount of improvement depended on the size of the mask patterns relative to that of their corresponding targets, set here by varying the intensity threshold for the images during mask optimization. Differences in how the images of the four types of masks changed with defocus were statistically insignificant.