Lionel Bening

Developments in Logic Network Path Delay Analysis

This paper discusses path delay analysis programs as an alternative to detailed logic simulation for finding timing problems in logic networks. Fundamentals of path delay analysis are reviewed, and several previously reported methods are surveyed. This is followed by a more detailed description of a delay analysis program that we have recently implemented. Our implementation uncovers a wide variety of timing problems and has a run time that is linearly proportional to the number of gates in the network. Other principle features are that timing information loss is minimized by treating 0-to-1 and 1-to-0 delays separately, and the user is given the capability of selectively disabling paths in order to discover timing problems that would otherwise remain hidden.

A two-state methodology for RTL logic simulation

This paper describes a two-state methodology for register transfer level (RTL) logic simulation in which the use of the X-state is completely eliminated inside ASIC designs. Examples are presented to show the gross pessimism and optimism that occurs with the X in RTL simulation. Random two-state initialization is offered as a way to detect and diagnose startup problems in RTL simulation. Random two-state initialization (a) is more productive than the X-state in gate-level simulation, and (b) provides better coverage of startup problems than X-state in RTL simulation. Consistent random initialization is applied (a) as a way to duplicate a startup state using a slower diagnosis-oriented simulator after a faster detection-oriented simulator reports the problem, and (b) to verify that the problem is corrected for that startup state after the design change intended to fix the problem. In addition to combining the earlier ideas of two-state simulation, and random initialization with consistent values across simulations, an original technique for treatment of tri-state Zs arriving into a two-state model is introduced.

Accurate simulation of high speed computer logic

This paper presents a design verification logic simulation system which uses a ccurate timing information and propagation delay ambiguity in its circuit models. The case in favor of such a system is put forth. Methods for simulating propagation delay ambiguity and utilizing accurate circuit timing data are introduced. The time-sequenced simulation programming technique used in this system is described. Host computer memory and time requirement data from simulation test runs are reported.

Optimizing multiple EDA tools within the ASIC design flow

Selecting a single register transfer level (RTL) coding style-one that maximizes the performance of simulation, Boolean equivalence, and model checking while achieving an optimal flow through synthesis and physical design-is a formidable task. To reconcile competing tool-coding requirements, the Hewlett-Packard Richardson VLSI Lab has developed a coding style and a design flow methodology that incorporates modern programming language principles. Using the principles of information hiding, abstraction, and encapsulation on all functional grouping of state elements (and other objects), our engineers can focus on design functionality rather than on each individual electronic design automation (EDA) tools optimal coding style requirement. Building on these principles, we have developed a design methodology to automate the generation of tool-specific libraries. This methodology, which optimizes multiple process points within the application-specific integrated circuit (ASIC) design flow, has several advantages: It permits a seamless optimization of design processes throughout the course of design and enables augmentation of new processes. It leaves the designers text and functional intent undisturbed throughout the designs duration. It offers cooperation and support for multiple EDA tools while achieving higher verification coverage in minimal time. Finally, our approach clarifies the design intent at the RTL, increases design productivity, and raises the abstraction level without forcing the designer to adopt a new hardware description language (I-IDL).

Application of a logic fault analyzer to the manufacture and maintenance of the CONTROL DATA 7600 computer

This paper describes the application of a sequential logic fault analyzer computer program to the problem of logic circuit module tests for the CONTROL DATA® 7600 computer. A description of the sequential fault analyzer is provided first. Next, the software system built around this fault analyzer is outlined. The development of test sequences for 231 logic module types used in the 7600 computer is considered. Block diagrams of the test fixtures used at the manufacturing facility and to supplement field maintenance are provided and explained. Preliminary results of the application of fault analyzer developed tests are reported.