Harry Foster

Assertions Targeting A Diverse Set of Verification Tools

A myriad of proprietary (i.e., commercial tool specific) verification assertion languages exist today. These languages emerged due to the lack of formal language constructs supporting assertion specification in today’s hardware description languages (HDL). The method described in this paper presents a unique process for unifying (or neutralizing the effects of) the many proprietary languages by using a set of predefined specification modules instantiated as assertions within the designer’s HDL. This methodology creates numerous advantages and precludes the need to introduce new HDL constructs (i.e., extensions to Verilog are not required). It enables the design engineer to “specify once,” then leverage the same HDL assertion specification over multiple verification processes -- such as traditional simulation, semi-formal, and formal verification tools. It also eliminates the need for the design engineer to master tool specific and proprietary language details. Furthermore, this methodology enables evaluating new verification processes and tools (containing their own proprietary languages) seamlessly for the duration of the project, without the need to modify the original HDL text.

Optimizing multiple EDA tools within the ASIC design flow

Selecting a single register transfer level (RTL) coding style-one that maximizes the performance of simulation, Boolean equivalence, and model checking while achieving an optimal flow through synthesis and physical design-is a formidable task. To reconcile competing tool-coding requirements, the Hewlett-Packard Richardson VLSI Lab has developed a coding style and a design flow methodology that incorporates modern programming language principles. Using the principles of information hiding, abstraction, and encapsulation on all functional grouping of state elements (and other objects), our engineers can focus on design functionality rather than on each individual electronic design automation (EDA) tools optimal coding style requirement. Building on these principles, we have developed a design methodology to automate the generation of tool-specific libraries. This methodology, which optimizes multiple process points within the application-specific integrated circuit (ASIC) design flow, has several advantages: It permits a seamless optimization of design processes throughout the course of design and enables augmentation of new processes. It leaves the designers text and functional intent undisturbed throughout the designs duration. It offers cooperation and support for multiple EDA tools while achieving higher verification coverage in minimal time. Finally, our approach clarifies the design intent at the RTL, increases design productivity, and raises the abstraction level without forcing the designer to adopt a new hardware description language (I-IDL).

Applied Boolean equivalence verification and RTL static sign-off

The author explores applying formal Boolean equivalence verification to the RTL design flow, and introduces an effective equivalence-checking usage model that ensures optimal benefits in an RTL static sign-off methodology.

Exception handling in microprocessors using assertion libraries

In complex system-on-a-chip (SoC) designs, designers often need to add new features into an original processor core, such as to extend the exception handling mechanism to consider exceptions in the remaining portion of the SoC design. We present in this paper a scalable architecture that can be used to add complex exception handling mechanisms in processor cores and how it can be used to extend the fixed set of exceptions found in microprocessor cores. This mechanism is based on the use of assertion libraries linked by an assertion processor to incorporate these new functionalities.

On-Chip Property Verification Using Assertion Processors

White-box verification is a technique that reduces observability problems by locating a failure during design simulation without the need to propagate the failure to the I/O pins. White-box verification in chip level designs can be implemented using assertion checkers to ensure the correct behavior of a design. With chip gate counts growing exponentially, today’s verification techniques, such as white-box, can not always ensure a bug free design. This paper proposes an assertion processor to be used with synthesized assertion checkers in released products to enable intelligent debugging of deployed designs. Extending white-box verification techniques to deployed products helps locate errors that were not found during simulation / emulation phases. We present results of the insertion of assertion checkers and an assertion processor in an 8-Bit processor and a communication core.