Lionel J. D'Luna

A digital video signal processor for color image sensors

The authors describe signal processor (DSP) for CCD (charge-coupled-device) cameras using a specified color filter array pattern. A block diagram of the DSP chip is shown. The chip has been designed and fabricated in a 2- mu m single-poly double-metal CMOS process. Eight scan-test registers were used at selected points in the processing chain to enable the entire chip to be tested, including ROMs and line delays, with 16 k vectors. The chip is functional at a maximum clock rate of 14.3 MHz. An image processed by the device is shown. The data path is designed with simple ripple-carry adders and dynamic registers. The on-chip programmable delay lines and 14.3-MHz clock-rate allow the chip to accommodate sensors for up to 768 active pixels, making it suitable for NTSC, CCIR 601 and PAL video standards.<<ETX>>

A digital color CCD imaging system using custom VLSI circuits

The authors describe a prototype digital imaging system that can be configured as a single-sensor video camera or a film-to-video converter. The system includes a CCD (charge-coupled device) image sensor with a 3G color filter pattern, two full-custom CMOS digital video signal processing chips, and a custom electronically programmable sequencer chip. The CMOS VLSI digital circuits offer real-time operation while meeting the size, power, and cost constraints of one-chip cameras and fill-to-video converters. System timing and design methodology are discussed. >

A digital video signal post-processor for color image sensors

A description is given of a digital-video-signal postprocessing chip (DSPP) developed for use with one-chip color video image sensors. The chip improves the image quality of reconstructed RGB data by performing black-level adjustment, color correction matrixing, gamma correction, and edge enhancement. It contains 115000 transistors in a 11.5 mm×11.2 mm die area and was designed using a silicon compiler in a 2-μm die area and was designed using a silicon compiler in a 2-μm CMOS process. It can be used in NTSC, CCIR 601, and PAL/SECAM video systems

A digital signal processor for linear sensors

A 132 K transistor device which performs black-level, gain, and defect corrections, line-rephasing, color matrixing, and curve-shaping functions on linear sensor data while interfacing to external memory and a data bus is described. The 2 mu m CMOS chip can be used with a wide range of sensor resolutions for various image-scanning applications. The chip performs the following functions: digital correlated double sampling, black-level correction and gain correction for each photosite, sensor defect concealment, color matrixing, and look-up table operations for space transformations. Additionally, three interface circuits are implemented to store and retrieve black-level and gain correction values, rephase red, green, and blue values to provide line coincidence, and function as a simple computer for loading coefficients and writing the processed image data.<<ETX>>

A serial/parallel color matrix, 2D convolution and 9-Tap filter ASIC with a systems perspective

A single chip that can perform three-channel 1*4 serial color matrixing, 3*4 color matrixing, 3*3 (2-D) convolution, and a nine-TAP FIR filter has been designed in a 1- mu m gate array. The chip operates at 25 MHz and is useful for color optimization in scanning applications using linear CCD sensors, in electronic imaging applications using area sensors, and in a variety of image processing applications such as edge direction, enhancement, filtering and precompression processing.<<ETX>>

An 8*8 discrete cosine transform chip with pixel rate clocks

Image compression is an established means of meeting storage and transmission requirements for image data. One method is transform domain compression using the two-dimensional discrete cosine transform (DCT) on 8*8 image blocks. A 2- mu m CMOS chip that computes this transform in real-time using clocks that are no faster than the pixel rate is described. The architecture uses a distributed arithmetic processing scheme to compute two one-dimensional transforms interposed with an unconventional matrix transpose RAM. The design methodology that includes layout, simulation, verification and test, using a silicon compiler tool-set, is described.<<ETX>>

A customizable timing controller for electronic imaging applications

The authors describe a programmable video timing and control ASIC (application-specific integrated circuit) that was designed in a fully custom manner using a silicon compiler tool set. The device architecture is specifically tailored to addressing the system requirements of video and other electronic imaging systems, incorporating genlock and defect correction functions. Customization requires only a VIA mask change, allowing the base architecture to be fabricated in advance, like a gate array. Fabrication turnaround time is less than that of a gate array and design effort redundancy is completely eliminated, providing a timely and cost-effective implementation. Designed in 2- mu m CMOS with 20-MHz operation, the device can be used in NTSC, CCIR 601, and PAL/SECAM video systems, but its flexible architecture makes it suitable for use in a wide variety of other applications as well.<<ETX>>