Liu Leibo

Design of wireless multi-media sensor network for precision agriculture

To satisfy the needs of modern precision agriculture, a Precision Agriculture Sensing System (PASS) is designed, which is based on wireless multi-media sensor network. Both hardware and software of PASS are tailored for sensing in wide farmland without human supervision. A dedicated single-chip sensor node platform is designed specially for wireless multi-media sensor network. To guarantee the bulky data transmission, a bitmap index reliable data transmission mechanism is proposed. And a battery-array switching system is design to power the sensor node to elongate the lifetime. The effectiveness and performance of PASS have been evaluated through comprehensive experiments and large-scale real-life deployment.

Reconfigurable cryptographic processor

The present invention discloses a reconfigurable cryptographic processor. The reconfigurable cryptographic processor is characterized by comprising: a configuration module, for acquiring and assigning a configuration parameter; a transmission module, for transmitting to-be-processed data according to the assigned configuration parameter; a processing module, for obtaining processed data and transmitting the processed data to the transmission module to output, wherein the processing module comprises an array operation cache for storing intermediate data and interaction data; a reconfigurable array, for realizing the operation, wherein each reconfigurable unit has a token driver enabling end for token enabling; and an asynchronous driver enabling network, for obtaining a token enabling network according to the assigned configuration parameter to provide a data jumping and transmission mode of the operation and to complete driving of the reconfigurable array, so as to control the reconfigurable cryptographic processor to enter into a corresponding working mode. According to the reconfigurable cryptographic processor provided by the embodiment of the present invention, the driver execution process is enabled by using the token, so that flexibility and execution performance are improved, power consumption is reduced, and security and reliability are better ensured.

Design and implementation of a reconfigurable SoC for high-definition video applications

This paper proposes a reconfigurable SoC architecture based on a large-scale reconfigurable processing elements (PEs) array, a high-performance RISC core and several embedded peripherals on-chip, which are coupled tightly through System buses of AMBA2.0. The large-scale PEs array is used to process video signals with different standards under appropriate contexts disposed dynamically. The embedded peripherals are with responsibility for the input of media stream data and output of the decoded multimedia data to display, while the RISC core takes charge of the initialization of the peripherals and the reconfigurable PEs, the pretreatment of media stream data, the audio decoding, the synchronization between audio and video data, and some other scheduling functions. The antitype SoC chip is implemented based on 65nm CMOS silicon techniques, and the testing results show that the reconfigurable SoC achieves the performance of real-time decoding of videos with size of 1920*1080 @ 30fps which follow the H.264, AVS and MPEG-2 standards respectively.

Key techniques of recon gurable computing processor

This paper rst analyzes the issues of the traditional instruction-driven and data-driven processors, as well as the trend of the recon gurable computing processor. Afterwards, hardware architecture and the compiler techniques of the recon gurable computing processor are discussed, focusing on the challenges facing the HW/SW architecture as well as the corresponding applications. Then, a recon gurable media processor, called REMUS (REcon gurable MUltimedia System), and its development tools are proposed. Finally, the vision of the generalpurpose recon gurable computing is presented.