Wei Shaojun

Design of wireless multi-media sensor network for precision agriculture

To satisfy the needs of modern precision agriculture, a Precision Agriculture Sensing System (PASS) is designed, which is based on wireless multi-media sensor network. Both hardware and software of PASS are tailored for sensing in wide farmland without human supervision. A dedicated single-chip sensor node platform is designed specially for wireless multi-media sensor network. To guarantee the bulky data transmission, a bitmap index reliable data transmission mechanism is proposed. And a battery-array switching system is design to power the sensor node to elongate the lifetime. The effectiveness and performance of PASS have been evaluated through comprehensive experiments and large-scale real-life deployment.

A low power 8-bit successive approximation register A/D for a wireless body sensor node

A power efficient 8-bit successive approximation register (SAR) A/D for the vital sign monitoring of a wireless body sensor network (WBSN) is presented. A charge redistribution architecture is employed. The prototype A/D is fabricated in 0.18 μm CMOS. The A/D achieves 7.5 ENOB with sampling rate varying from 64 kHz to 1.5 MHz. The power consumption varies from 10.8 to 225.7 μW.

Energy-aware supply and body biasing voltage scheduling algorithm

A technique of energy minimization by combining dynamic voltage scheduling (DVS) and adaptive body biasing voltage (ABB) method for distributed real-time system at system design level is proposed. Based on a simplified energy optimizing model, the proposed approach named LEVVS (low energy supply voltage and body biasing voltage scheduling algorithm) explores the minimizing of energy consumption by finding optimal trade-off between dynamic and static energy. Experiments show that, using the LEVVS approach, more than 53% average energy reduction can be obtained than by employing the DVS method alone. Furthermore the effects of switch capacitance and global slack on the energy saving efficiency of LEVVS are investigated.

Reconfigurable cryptographic processor

The present invention discloses a reconfigurable cryptographic processor. The reconfigurable cryptographic processor is characterized by comprising: a configuration module, for acquiring and assigning a configuration parameter; a transmission module, for transmitting to-be-processed data according to the assigned configuration parameter; a processing module, for obtaining processed data and transmitting the processed data to the transmission module to output, wherein the processing module comprises an array operation cache for storing intermediate data and interaction data; a reconfigurable array, for realizing the operation, wherein each reconfigurable unit has a token driver enabling end for token enabling; and an asynchronous driver enabling network, for obtaining a token enabling network according to the assigned configuration parameter to provide a data jumping and transmission mode of the operation and to complete driving of the reconfigurable array, so as to control the reconfigurable cryptographic processor to enter into a corresponding working mode. According to the reconfigurable cryptographic processor provided by the embodiment of the present invention, the driver execution process is enabled by using the token, so that flexibility and execution performance are improved, power consumption is reduced, and security and reliability are better ensured.

A 1.1 mW 87 dB dynamic range Δ σ modulator for audio applications

This paper presents a 1.1 mW 87 dB dynamic range third order Δ σ modulator implemented in 0.18 μm CMOS technology for audio applications. By adopting a feed-forward multi-bit topology, the signal swing at the output of the first integrator can be suppressed. A simple current mirror single stage OTA with 34 dB DC gain working under 1 V power supply is used in the first integrator. The prototype modulator achieves 87 dB DR and 83.8 dB peak SNDR across the bandwidth from 100 Hz to 24 kHz with 3 kHz input signal.

Optimizing SoC platform architecture for multimedia applications

As system-on-chip (SoC) will soon become the whole world electronic production mainstream in the near future, Datang Microelectronics Technology Co., LTD., Beijing, China, is now focusing on SoC platform based hardware designs and software applications as a pioneer. In this paper, a typical research case is described on how to optimizing a SoC architecture for multimedia applications. ConvergenSC, one of CoWare Corporations electronic system level design tool, helped us greatly on structuring a series virtual SoC architectures, and then quickly getting all kinds of performance analysis results according to the corresponding virtual SoC architecture. With its aids, we easily got our best design result

Key techniques of recon gurable computing processor

This paper rst analyzes the issues of the traditional instruction-driven and data-driven processors, as well as the trend of the recon gurable computing processor. Afterwards, hardware architecture and the compiler techniques of the recon gurable computing processor are discussed, focusing on the challenges facing the HW/SW architecture as well as the corresponding applications. Then, a recon gurable media processor, called REMUS (REcon gurable MUltimedia System), and its development tools are proposed. Finally, the vision of the generalpurpose recon gurable computing is presented.

Battery Aware Variable Voltage Task Scheduling for System Energy Consumption Minimization

Optimization of battery energy consumption by variable voltage task scheduling technique is studied in the paper. An efficient slack time allocation policy is firstly derived by comprehensive analysis on non-linear characteristics of battery. In further, two heuristic BATS (battery aware task scheduling) algorithms are proposed. The former takes the task discharge current as the priority function for slack time allocation, hence can reduce the peak power efficiently, while the later takes the task discharge current weighted by execution time as the priority function, hence can optimize the battery energy consumption more efficiently. Experiment results show that the proposed algorithms can greatly reduce the battery energy consumption by more than 30% and the peak power of the system simultaneously

Energy minimizing by DVS for distributed real-time systems

Technique of energy minimization by dynamic voltage scheduling (DVS) for distributed real-time system at system level design is proposed. Considering variation of power profile and degree of parallelism simultaneously while allocating slack time, the proposed approach named LEDS explores space of minimizing energy consumption. Experiments show that using LEDS approach, 33.5% higher energy reduction can be obtained than previous method.Technique of energy minimization by dynamic voltage scheduling (DVS) for distributed real-time system at system level design is proposed. Considering variation of power profile and degree of parallelism simultaneously while allocating slack time, the proposed approach named LEDS explores space of minimizing energy consumption. Experiments show that using LEDS approach, 33.5% higher energy reduction can be obtained than previous method.

Design and application of ATM-SDH multiplex/demultiplex ASIC

The combination of ARM and SDH is of great importance in the future high speed telecommunication network. In our work, we pointed out the need of the low speed ATM transmission through SDH, analyzed the system requirement planned an ASIC to implement the ATM-SDH multiplex/demultiplex system, designed the chip architecture, described the chip using VHDL coding, and implemented the chip by ALTERA FPGA. Several possible application configurations using the ASIC and the chip verification system are also introduced.