Livia M. Racz

Demonstration of a novel hybrid silicon-resin high density interconnect (HDI) substrate

We examine the thermomechanical tradeoffs in a novel technology for high density interconnect (HDI) substrates. Fabricated from silicon (Si) wafers with planar cavities of highly-filled composite encapsulant, the technology leverages established Si photolithography but offers improved mechanical properties. Modules are subject to thermomechanical stress during encapsulant cure, assembly reflow, module fabrication, and operation. We show that improvements in junction-to-ambient sinking offset the heat density increase in such systems and low expansion encapsulants prevent failure during cure. We employ finite element modeling and materials testing to show the effect of wafer design and material selection on the stresses in the module.

Thermal and Mechanical Considerations for Silicon-Resin High-Density Substrate

We examine the thermomechanical tradeoffs in a novel technology for high-density interconnect substrates. Fabricated from silicon (Si) wafers with planar cavities of highly filled composite encapsulant, the technology leverages established Si photolithography but offers improved mechanical properties. Modules are subject to thermomechanical stress during encapsulant cure, assembly reflow, module fabrication, and operation. We show that improvements in junction-to-ambient sinking offset the heat density increase in such systems and low expansion encapsulants prevent failure during cure and subsequent processing. We employ finite element modeling and materials testing to show the effect of wafer design and material selection on the in-plane and through-plane stresses in the module.

A Multistep Process for Thinning Individual Die to sub-35 μm Thickness

The drive toward increased packaging density relies on die stacking. In order to maximize functional density, die are generally thinned on the wafer level. However, high-cost low-volume applications may not have full wafers available. Therefore, a method to thin individual die must be developed. In this article, a detailed and reliable process for thinning die to sub35 μm is outlined. The process consists of four steps: pseudo-wafer lamination, mechanical lapping, chemical mechanical planarization (CMP), and die release. A pseudo-wafer is created by adhering die to a glass substrate. Mechanical lapping is used to remove the bulk silicon and reduce die thickness to approximately 50 μm. CMP is used to attain thicknesses of sub35 μm and remove the subsurface damage layer from the die. This process can reliably produce die thinned to sub35 μm with ± 1.5-μm total thickness variation (TTV). The die are then released from the glass substrate and are handled using a customized vacuum carrier.

A Method for Die Thickness Reduction to sub-35 μm

Significant system performance improvements can be realized by stacking die layers. This approach, known as 3-D integration, can reduce RC delay as well as the system form factor. Die are typically thinned in wafer form prior to integration into the modules allowing even greater functional density. However, certain applications require the thinning of individual die. A detailed technique including die lamination, lapping, chemical mechanical planarization (CMP), and release has been developed to thin die to 35 μm thickness. During lamination, the die are temporarily adhered with their active side down to a glass substrate using an adhesive. Mechanical lapping is performed to remove the majority of silicon from the back side. The final thickness of approximately 35 μm is achieved using CMP. The CMP step is critical for the removal of sub-surface damage and prevention of device failure. After thinning, the adhesive is dissolved and the die are handled using porous end effectors. The process can effectively produce die thinned to 35 μm with ± 1.5 μm total thickness variation (TTV).