Thomas A. Langdo

Controlling threading dislocation densities in Ge on Si using graded SiGe layers and chemical-mechanical polishing

A method of controlling threading dislocation densities in Ge on Si involving graded SiGe layers and chemical-mechanical polishing (CMP) is presented. This method has allowed us to grow a relaxed graded buffer to 100% Ge without the increase in threading dislocation density normally observed in thick graded structures. This sample has been characterized by transmission electron microscopy, etch-pit density, atomic force microscopy, Nomarski optical microscopy, and triple-axis x-ray diffraction. Compared to other relaxed graded buffers in which CMP was not implemented, this sample exhibits improvements in threading dislocation density and surface roughness. We have also made process modifications in order to eliminate particles due to gas-phase nucleation and cracks due to thermal mismatch strain. We have achieved relaxed Ge on Si with a threading dislocation density of 2.1×106 cm−2, and we expect that further process refinements will lead to lower threading dislocation densities on the order of bulk Ge su...

Carrier mobilities and process stability of strained Si n- and p-MOSFETs on SiGe virtual substrates

Surface channel strained Si metal–oxide–semiconductor field-effect transistors (MOSFETs) are a leading contender for future high performance complementary metal–oxide–semiconductor (CMOS) applications. The carrier mobility enhancement of these devices is studied as a function of channel strain, and the saturation behavior for n- and p-channel devices is compared. Carrier mobility enhancements of up to 1.8 and 1.6 are achieved for n- and p-channel devices, respectively. The process stability of strained Si MOSFETs is also studied, and carrier mobility enhancement is shown to be robust after well implantation and virtual substrate planarization steps. The effects of high-temperature implant activation anneals are also studied. While no misfit dislocation introduction or strain relaxation is observed in these devices, increased interface state densities or alloy scattering due to Ge interdiffusion are shown to decrease mobility enhancements. Channel thickness effects are also examined for strained Si n-MOSFE...

Strained Ge channel p-type metal–oxide–semiconductor field-effect transistors grown on Si1−xGex/Si virtual substrates

We have fabricated strained Ge channel p-type metal–oxide–semiconductor field-effect transistors (p-MOSFETs) on Si0.3Ge0.7 virtual substrates. The poor interface between silicon dioxide (SiO2) and the Ge channel was eliminated by capping the strained Ge layer with a relaxed, epitaxial silicon surface layer grown at 400 °C. Ge p-MOSFETs fabricated from this structure show a hole mobility enhancement of nearly eight times that of co-processed bulk Si devices, and the Ge MOSFETs have a peak effective mobility of 1160 cm2/V s. These MOSFETs demonstrate the possibility of creating a surface channel enhancement-mode MOSFET with buried channel-like transport characteristics.

High quality Ge on Si by epitaxial necking

We show that pure Ge grown selectively on SiO2/Si substrates in 100 nm holes is highly perfect at the top surface compared to conventional Ge lattice-mismatched growth on planar Si substrates. This result is achieved through a combination of interferometric lithography SiO2/Si substrate patterning and ultrahigh vacuum chemical vapor deposition Ge selective epitaxial growth. This “epitaxial necking,” in which threading dislocations are blocked at oxide sidewalls, shows promise for dislocation filtering and the fabrication of low-defect density Ge on Si. Defects at the Ge film surface only arise at the merging of epitaxial lateral overgrowth fronts from neighboring holes. These results confirm that epitaxial necking can be used to reduce threading dislocation density in lattice-mismatched systems.

Dislocation dynamics in relaxed graded composition semiconductors

Abstract Lattice-mismatched relaxed graded composition layers in the SiGe/Si, InGaAs/GaAs, and InGaP/GaP systems have recently been created with unprecedented high quality due to advances in understanding the impact of epitaxial growth conditions. The key process–property correlation is the impact of growth conditions on dislocation dynamics. In particular, the SiGe/Si system has recently been well explored experimentally, allowing the dislocation dynamic model to be tested. We show that the dislocation dynamics model is in general applicable to graded layers in any material system as long as dislocation flow is not impeded. In the SiGe/Si, InGaAs/GaAs, and InGaP/GaP systems, with moderately dislocated graded layers, these mechanisms can be absent under appropriate growth conditions. However, in all systems, threading dislocation impediments eventually occur under continued deformation through continued grading. The mechanism in SiGe/Si is related to the impediment of dislocation flow from the surface morphology and strain-fields from misfit dislocations. In the III–V systems, we observe that a planar defect, referred to here as branch defects, can form under a wide range of growth conditions, and these defects will lead to inhibited dislocation flow. The quantitative nature of these effects can be empirically modeled with the same dislocation dynamic model by incorporating a composition-dependent change in the effective strain experienced by threading dislocations during grading-induced deformation.

HIGH-QUALITY GERMANIUM PHOTODIODES INTEGRATED ON SILICON SUBSTRATES USING OPTIMIZED RELAXED GRADED BUFFERS

The integration of Ge photodetectors on silicon substrates is advantageous for various Si-based optoelectronics applications. We have fabricated integrated Ge photodiodes on a graded optimized relaxed SiGe buffer on Si. The dark current in the Ge mesa diodes, Js=0.15 mA/cm2, is close to the theoretical reverse saturation current and is a record low for Ge diodes integrated on Si substrates. Capacitance measurements indicate that the detectors are capable of operating at high frequencies (2.35 GHz). The photodiodes exhibit an external quantum efficiency of η=12.6% at λ=1.3 μm laser excitation in the photodiodes. The improvement in Ge materials quality and photodiode performance is derived from an optimized relaxed buffer process that includes a chemical mechanical polishing step within the dislocated epitaxial structure.

Relaxed template for fabricating regularly distributed quantum dot arrays

Relaxed SiGe thin films are used as templates to control the nucleation of three-dimensional Ge islands on Si(100) substrates. Using the relaxed template, Ge islands form a rectangular array with all islands located exclusively above the intersections of dislocations. The registration is lost when the Ge growth temperature is lowered to 300 °C, and the Ge coverage is decreased to 0.4 nm.

Film thickness constraints for manufacturable strained silicon CMOS

This paper studies the effect of the strained silicon thickness on the characteristics of strained silicon MOSFETs on SiGe virtual substrates. NMOSFETs were fabricated on strained silicon substrates with various strained silicon thicknesses, both above and below the strained silicon critical thickness. The low field electron mobility and subthreshold characteristics of the devices were measured. Low field electron mobility is increased by about 1.8 times on all wafers and is not significantly degraded on any of the samples, even for a strained silicon thickness far greater than the critical thickness. From the subthreshold characteristics, however, it is shown that the off-state leakage current is greatly increased for the devices on the wafers with a strained silicon thickness that exceeds the critical thickness. The mechanism of the leakage was examined by using photon emission microscopy. Strong evidence is shown that the leakage mechanism is source/drain electrical shorting caused by enhanced dopant diffusion near misfit dislocations.

SiGe-free strained Si on insulator by wafer bonding and layer transfer

SiGe-free strained Si on insulator substrates were fabricated by wafer bonding and hydrogen-induced layer transfer of strained Si grown on bulk relaxed Si0.68Ge0.32 graded layers. Raman spectroscopy shows that the 49-nm thick strained Si on insulator structure maintains a 1.15% tensile strain even after SiGe layer removal. The strain in the structure is thermally stable during 1000 °C anneals for at least 3 min, while more extreme thermal treatments at 1100 °C cause slight film relaxation. The fabrication of epitaxially defined, thin strained Si layers directly on a buried insulator forms an ideal platform for future generations of Si-based microelectronics.

High minority-carrier lifetimes in GaAs grown on low-defect-density Ge/GeSi/Si substrates

A high bulk minority-carrier lifetime in GaAs grown on Si-based substrates is demonstrated. This was achieved by utilizing a step-graded Ge/GeSi buffer (threading dislocation density 2×106 cm−2) grown on an offcut (001) Si wafer, coupled with monolayer-scale control of the GaAs nucleation to suppress antiphase domains. Bulk minority-carrier lifetimes (τp) were measured using room-temperature time-resolved photoluminescence applied to a series of Al0.3Ga0.7As/GaAs/Al0.3Ga0.7As double-heterojunction structures doped n=1.1×1017 cm−3 with GaAs thicknesses of 0.5, 1.0, and 1.5 μm. A lifetime τp=7.7 ns was determined for GaAs grown on Si. The extracted interface recombination velocity of 3.9×103 cm/s is comparable to recombination velocities found for Al0.3Ga0.7As/GaAs interfaces grown on both GaAs and Ge wafers, indicating that the crosshatch surface morphology characteristic of strain-relaxed Ge/GeSi surfaces does not impede the formation of high-electronic-quality interfaces. These results hold great promise...