Loai G. Salem

4.6 An 85%-efficiency fully integrated 15-ratio recursive switched-capacitor DC-DC converter with 0.1-to-2.2V output voltage range

The growing demand for both performance and battery life in portable consumer electronics requires SoCs and power management circuits to be small, efficient, and dynamically powerful. Dynamic voltage scaling (DVS) can help achieve these goals in load circuits, though generally at the expense of increased DC-DC converter size (through use of external inductors) or loss (through linear regulation). While switched-capacitor (SC) DC-DC converters can offer conversion in small fully integrated form factors [1-5], their efficiencies are only high at discrete ratios between the input and output voltages. To increase an SC converter efficiency across its output voltage range, multiple conversion ratios can be utilized to realize a finer output voltage resolution. For instance, many converters employ a small handful of conversion ratios [1-4]. However, more conversion ratios are generally necessary to achieve high efficiency across the wide output range necessary for DVS, as converter efficiencies can otherwise fall by more than 20% between unloaded ratios [1-4]. Unfortunately, increasing the number of ratios beyond a small handful using standard topologies can significantly increase the number of components, escalating converter complexity and adding losses in the additional switching elements. To overcome this, a successive approximation (SAR) SC topology was proposed in [6] which cascades several 2:1 SC stages to provide a large number of conversion ratios with minimal hardware overhead. However, the linear cascading of stages introduces cascaded losses, limiting overall efficiency. For example, the minimum Rout is more than 30X Rout of a similar ratio Series-Parallel topology using the same silicon area. Additionally, current density is limited to that of a single stage, and capacitance utilization can be low for many conversion ratios.

A Recursive Switched-Capacitor DC-DC Converter Achieving

A Recursive Switched-Capacitor (RSC) topology is introduced that enables reconfiguration among 2 N-1 conversion ratios while achieving minimal capacitive charge-sharing loss for a given silicon area. All 2 N-1 ratios are realized by strategically interconnecting N 2:1 SC cells either in series, in parallel, or in a stacked configuration such that the number of input and ground connections are maximized in order to minimize cascaded losses. Importantly, all ratios are dynamically reconfigurable without disconnecting a single capacitor, all while ensuring optimal capacitance/conductance relative-sizing. The RSC topology is inherently regular, enabling recursive inter-cell connection and recursive binary-slicing that implement ratio-reconfiguration with minimum complexity and losses. A scalable all-digital binary search controller is employed to perform ratio-reconfiguration among the available 2 N-1 ratios without using any ratio-threshold generation circuitry. To validate the topology, a 4 bit RSC is fully integrated in 0.25 μm bulk CMOS using MIM capacitors, achieving greater than 70% efficiency over a 0.8-2.2 V output voltage range with 85.8% peak-efficiency from a 2.5V input supply. Compared to a co-fabricated three-ratio (1/3, 1/2, 2/3) Series-Parallel SC converter, the RSC achieves a 40.4% larger output operating range (from 0.04 to 2.2 V), and fills the efficiency-drops in-between the three-ratios by 8% with a 940 Ω load.

2^{N}-1

A Recursive Ternary switched-capacitor (RT-SC) topology that achieves more than 3(3^N-1)/2 ratios with N SC cells is presented. To achieve the high number of ratios for a wide output voltage range, a three-ratio (1/3, 1/2, 2/3) Series-Parallel (SP) topology is sliced into N reconfigurable three-ratio SP sub-cells that are interconnected in a series or stacked configuration in order to realize a minimum voltage-conversion resolution of V_in/6^N. Importantly, this modular approach supports a recursively defined topology, by operating the three-ratio SP sub-cells in parallel the high efficiency at large power density of a standard three-ratio SP converter is achieved. The proposed RT-SC converter realizes ternary m₃/3^N conversion ratios as well as binary m₂/2^N and mixing m₆/6^N-1 modes. A 45-ratio fully-integrated RT-SC is fabricated in a 0.25 μm CMOS process, achieving 53% larger output operating range than a conventional three-ratio SP at 0.5 mA/mm², and 15% higher efficiency than a Recursive Binary SC at 3.4× larger current density.

Ratios With High Efficiency Over a Wide Output Voltage Range

A switched-capacitor (SC) PMIC is presented that achieves up to a 6.6-bit resolution with only 5 flying capacitors for inductive PMIC replacement. The flying capacitors are reused in a frequency-scaled gear train as well as charge-feedback SC topologies to attain a 2.4× reduction in capacitors number compared to prior art. In 0.25μm bulk, the PMIC operates from an input voltage of 2.5-5V, can generate an output voltage ranging from 0.2-2V, and features an average efficiency of 90.2% across the entire range and a peak efficiency of 95.5%.

A 45-ratio recursively sliced series-parallel switched-capacitor DC-DC converter achieving 86% efficiency.

Modern SoC designs employed in battery-life-constrained mobile applications feature multiple power domains to dynamically scale power-performance trade-offs in response to application demands. Since each power domain requires a DC-DC converter, and since low-power mobile applications are also typically area-constrained, the employed DC-DC voltage regulators must: 1) be fully integrated, 2) support high efficiency across large dynamic current ranges spanning high-power active modes to low-power sleep modes where the overhead of complex control or multi-phasing is not feasible [1], and 3) support high power density to occupy minimal area overhead. Unfortunately, achieving both high efficiency and power density is difficult: integrated magnetic converters have limited efficiency and do not leverage CMOS scaling, while switched-capacitor (SC) converters suffer from fundamental power density-efficiency trade-offs due to ½C(ΔV)2f-based slow-switching-limit (SSL) losses. While recent work has employed high-density capacitors using ferroelectric or deep-trench technologies to achieve both high efficiency and high power density [2,3], such capacitor technologies are not available in all processes, and SSL losses still restrict the power density-efficiency trade-off, even with further scaling. Stacked-domain (SD) converters attempt to address this trade-off by achieving DC-DC conversion via stacked loads [4]; however, efficiency and density of SD converters approach the performance of the underlying charge-balance DC-DC converter required under load mismatch conditions, limiting the benefits of the SD approach for practical loads.

A battery-connected 24-ratio switched capacitor PMIC achieving 95.5%-efficiency

This paper introduces a modeling framework to predict the efficiency scaling of switched-capacitor (SC) dc-dc converters under power density constraints. A reference power density metric is introduced under which SC converters are integrated directly on silicon using the available decoupling capacitance without increasing the chip footprint. An analytical model is then employed to predict the scaled SC converter efficiency, where it is found that the efficiency scales inversely with the product of the chip clock frequency and the MOSFET intrinsic delay. Through a derived numerical model of the SC power density, it is shown that a ~ 0.5 W/mm2 SC density is sufficient to satisfy portable SoC power management needs with over 80% SC efficiency across the International Technology Roadmap for Semiconductors. This is at minimal area penalty by utilizing the nominally required 0.5 nF/mm2 decoupling capacitance for supply integrity.

12.9 A flying-domain DC-DC converter powering a Cortex-M0 processor with 90.8% efficiency

This paper demonstrates the first 7-ratio resonant switched capacitor (SC) converter using only a single inductor, realizing the widest resonant operating range reported in CMOS. A frequency-scaled gear train SC topology is introduced that enables soft-charging of all flying capacitors through one inductor at any arbitrary binary ratio by eliminating the inter-stage decoupling required in prior-art. Gear ratio modulation is proposed to control the resonance Q-factor, and hence the regulator can be gracefully transitioned from a resonant converter to a fully-capacitive SC, enabling > 24,000x output current range. For the same footprint, the converter achieves up to 14.4% and 12% efficiency improvements over co-fabricated SC and 3-level buck converters, respectively, while operating with a peak efficiency of 73.3% and current density of 0.14 A/mm2 in 0.18 μm bulk.

A footprint-constrained efficiency roadmap for on-chip switched-capacitor DC-DC converters

Modern subthreshold SoC designs feature multiple power domains to dynamically track the maximum energy-efficiency point (0.32–0.45V [1]) in response to application demands. While analog low-drop-out (LDO) regulators have shown rapid response times (e.g. TR = 0.65ns [2]) and excellent steady-state performance, they fail to operate at the low input voltages, VIN, typically supplied to such SoCs via either a high-efficiency switching DC-DC converter or an external harvesting source (e.g., VIN = 0.5V). On the other hand, digital LDOs (DLDOs) are becoming popular in low-voltage SoC designs where they can operate reliably from supplies down to 0.5V. However, conventional DLDOs respond slowly to large current steps, especially at low voltages (e.g., TR = ∼44ns, 57.1ns, and 4µs at VIN=1V [3–5], and 20µs at VIN=0.5V [1]). Furthermore, they suffer from limited dynamic range over which the load is regulated and stable (e.g. < 50× [1,4,5]) and occupy a large active area due to barrel-shifter-based control. While slow response can be mitigated with a higher sampling frequency, fs, this comes at increased power consumption and, importantly, reduced loop stability. To address these issues, this paper presents a 0.5V 0.0023mm2 recursive all-digital LDO (RLDO) in 65nm with hybrid PD-SAR and PWM duty control that achieves 15.1ns and 100ns response and settling times, respectively, while maintaining 5.6mV/mA load regulation and loop stability across a 20,000× dynamic load range, eclipsing state-of-the-art active area, response time, settling time, and dynamic range metrics across prior-art digital LDOs by over an order of magnitude.

A single-inductor 7+7 ratio reconfigurable resonant switched-capacitor DC-DC converter with 0.1-to-1.5V output voltage range

This paper presents a new power conversion method that can achieve both high efficiency and high power density by obviating the need for an area-consuming flying capacitor and replacing it with a flying digital load. The proposed flying-domain (FD) power conversion concept enables higher conversion efficiency than a conventional switched-capacitor converter by reducing charge-sharing and bottom-plate parasitic losses, while also enabling higher power density by eliminating the area occupied by the flying passive itself. This paper presents state-space analysis that shows that the proposed FD concept is well posed and reaches a valid steady state, while also presenting experimental results of several FD converters implemented in 180 nm SOI. With no flying passives, the fabricated FD converter achieves a peak efficiency of 99.2%, delivers up to 11.8 W/mm2 (2.3 W/mm2 with decoupling) at 91.7% efficiency, and can directly power a cofabricated Cortex M0 processor that communicates via flying I/O level shifters.

20.3 A 100nA-to-2mA successive-approximation digital LDO with PD compensation and sub-LSB duty control achieving a 15.1ns response time at 0.5V

Recent advancements in integrated radio design have enabled many new applications ranging from wearable health-care or fitness monitors to Internet of Things devices, structural integrity monitors, and beyond. In many of these applications, device size and battery life are of critical importance. Since radios often consume a significant portion of the power budget in small sensing nodes [1], reducing radio power consumption is an effective way to decrease battery size or increase battery life. Reducing radio power consumption can be challenging as there are important tradeoffs between power consumption and performance metrics such as radiated output power, linearity, sensitivity, channelization capabilities, and interference sensitivity. Low-power radio designs often sacrifice one or more of these metrics in the pursuit of low overall power consumption.