James F. Buckwalter

A Monolithic 25-Gb/s Transceiver With Photonic Ring Modulators and Ge Detectors in a 130-nm CMOS SOI Process

A fully-integrated, silicon photonic transceiver is demonstrated in a silicon-on-insulator process using photonic microring resonator modulators for low power consumption. The trade-offs between bandwidth and extinction ratio are discussed and motivate the use of transmit pre-emphasis for ring modulators to increase the interconnect data rate. The transmitter and receiver is demonstrated to data rates of 25 Gb/s with a BER of 10 ^-12. The total power consumption of the transceiver is 256 mW and demonstrates a link efficiency of 10.2 pJ/bit excluding laser power. At 25 Gb/s, the driver operates at 7.2 pJ/bit.

Cancellation of crosstalk-induced jitter

A novel jitter equalization circuit is presented that addresses crosstalk-induced jitter in high-speed serial links. A simple model of electromagnetic coupling demonstrates the generation of crosstalk-induced jitter. The analysis highlights unique aspects of crosstalk-induced jitter that differ from far-end crosstalk. The model is used to predict the crosstalk-induced jitter in 2-PAM and 4-PAM, which is compared to measurement. Furthermore, the model suggests an equalizer that compensates for the data-induced electromagnetic coupling between adjacent links and is suitable for pre- or post-emphasis schemes. The circuits are implemented using 130-nm MOSFETs and operate at 5-10 Gb/s. The results demonstrate reduced deterministic jitter and lower bit-error rate (BER). At 10 Gb/s, the crosstalk-induced jitter equalizer opens the eye at 10/sup -12/ BER from 17 to 45 ps and lowers the rms jitter from 8.7 to 6.3 ps.

Predicting data-dependent jitter

An analysis for calculating data-dependent jitter (DDJ) in a first-order system is introduced. The predicted DDJ features unique threshold crossing times with self-similar geometry. An approximation for DDJ in second-order systems is described in terms of the damping factor and natural frequency. Higher order responses demonstrate conditions under which unique threshold crossing times do not exist and total jitter is minimized. The DDJ predictions are verified with jitter measurements in a bandwidth-limited amplifier. The predictions for both first and second-order systems anticipate the features of the observed jitter.

Bandwidth Enhancement With Low Group-Delay Variation for a 40-Gb/s Transimpedance Amplifier

A 40-Gb/s transimpedance amplifier (TIA) is proposed using multistage inductive-series peaking for low group-delay variation. A transimpedance limit for multistage TIAs is derived, and a bandwidth-enhancement technique using inductive-series π -networks is analyzed. A design method for low group delay constrained to 3-dB bandwidth enhancement is suggested. The TIA is implemented in a 0.13-μm CMOS process and achieves a 3-dB bandwidth of 29 GHz. The transimpedance gain is 50 dB·Ω , and the transimpedance group-delay variation is less than 16 ps over the 3-dB bandwidth. The chip occupies an area of 0.4 mm2, including the pads, and consumes 45.7 mW from a 1.5-V supply. The measured TIA demonstrates a transimpedance figure of merit of 200.7 Ω/pJ.

Data-dependent jitter in serial communications

We present a method for predicting data-dependent jitter (DDJ) introduced by a general linear time-invariant LTI system based on the systems unit step response. We express the exact DDJ of a first-order system and verify the validity of the solution experimentally. We then propose a perturbation technique to generalize the analytical expression for DDJ. We highlight the significance of the unit step response in characterizing DDJ and emphasize that bandwidth is not a complete measure for predicting DDJ. We separate the individual jitter contributions of prior bits and use the result to predict the DDJ of a general LTI system. In particular, we identify a dominant prior bit that signifies the well-known distribution of deterministic jitter, the two impulse functions. We also show a jitter minimization property of high-order LTI systems. We verify our generalized analytical expression of DDJ for several real systems including an integrated CMOS 10-Gb/s trans-impedance amplifier by comparing the theory and measurement results. The theory predicts the jitter with as low as only 7.5% error.

A 40-Gb/s Optical Transceiver Front-End in 45 nm SOI CMOS

A low-power, 40-Gb/s optical transceiver front-end is demonstrated in a 45-nm silicon-on-insulator (SOI) CMOS process. Both single-ended and differential optical modulators are demonstrated with floating-body transistors to reach output swings of more than 2 VPP and 4 VPP, respectively. A single-ended gain of 7.6 dB is measured over 33 GHz. The optical receiver consists of a transimpedance amplifier (TIA) and post-amplifier with 55 dB ·Ω of transimpedance over 30 GHz. The group-delay variation is ±3.9 ps over the 3-dB bandwidth and the average input-referred noise density is 20.5 pA/(√Hz) . The TIA consumes 9 mW from a 1-V supply for a transimpedance figure of merit of 1875 Ω /pJ. This represents the lowest power consumption for a transmitter and receiver operating at 40 Gb/s in a CMOS process.

A Q-Band Amplifier Implemented with Stacked 45-nm CMOS FETs

A stacked FET, single-stage 45-GHz (Q-band) CMOS power amplifier (PA) is presented. The design stacked three FETs to avoid breakdown while allowing a high supply voltage. The IC was implemented in a 45-nm CMOS SOI process. The saturated output power exceeds 18 dBm from a 4-V supply. Integrated shielded coplanar waveguide (CPW) transmission lines as well as metal finger capacitors were used for input and output matching. The amplifier occupies an area of 450x500 im² including pads, while achieving a maximum power-added-efficiency (PAE) above 20%.

An active analog delay and the delay reference loop

Wireline signal processing circuits such as transversal equalizers rely on true time delay. An active analog delay stage is proposed that requires a sixteenth of the area of a comparable LC delay line. A delay reference loop is also presented to tune the delay stage against process, voltage, and temperature variations. A reference signal is introduced to tune the delay. The impact of non-idealities must be considered, to understand the relationship between the reference frequency and the locked time delay. A SiGe BiCMOS implementation of the active analog delay stage and delay reference loop is presented that operates to 10 Gb/s.

Phase and amplitude pre-emphasis techniques for low-power serial links

A novel approach to equalization of high-speed serial links combines both amplitude pre-emphasis to correct for intersymbol interference and phase pre-emphasis to compensate for deterministic jitter, in particular, data-dependent jitter. Phase pre-emphasis augments the performance of low power transmitters in bandwidth-limited channels. The transmitter circuit is implemented in a 90-nm bulk CMOS process and reduces power consumption by pushing CMOS static logic to the output stage, a 4:1 output multiplexer. The received signal jitter over a cable is reduced from 16.15 ps to 10.29 ps with only phase pre-emphasis at the transmitter. The jitter is reduced by 3.6 ps over an FR-4 backplane interconnect. A transmitter without phase pre-emphasis consumes 18 mW of power at 6Gb/s and 600mVpp output swing, a power budget of 3mW/Gb/s, while a transmitter with phase pre-emphasis consumes 24mW, a budget of 4 mW/Gb/s.

Data-dependent jitter and crosstalk-induced bounded uncorrelated jitter in copper interconnects

This paper resolves the jitter impairment of non-return-to-zero data in transmission lines. The limited bandwidth of the transmission line introduces data-dependent jitter. Crosstalk between neighbouring lines results in bounded uncorrelated jitter in the data eye. An analytical approach to representing data-dependent jitter and crosstalk-induced bounded uncorrelated jitter is presented. Comparison with jitter measurements of microstrip lines on FR4 board demonstrated accuracy to within 15% of the predictions for deterministic jitter.