Qinsong Qian

Repetitive Unclamped-Inductive-Switching-Induced Electrical Parameters Degradations and Simulation Optimizations for 4H-SiC MOSFETs

In this paper, the electrical parameter degradations of high-voltage 4H-SiC MOSFETs under repetitive unclamped-inductive-switching (UIS) stresses were investigated experimentally. The holes injection and trapping into the gate oxide above the JFET region is identified to be the main degradation mechanism, resulting in the increase of OFF-state drain-source leakage current (IDSS) and the decrease of ON-state resistance (Rdson). However, during the repetitive UIS stresses, there is not obvious degradation observed for the threshold voltage (Vth) of the device. Moreover, three improved SiC MOSFETs structures, one with step gate oxide above the JFET region, one with step p-body region, and another one with floated shallow p-well in the middle of JFET region, were proposed to reduce the degradations under the repetitive UIS stresses.

The Investigation of Electrothermal Characteristics of High-Voltage Lateral IGBT for ESD Protection

In this paper, the detailed characterizations of the lateral insulated-gate bipolar transistor (LIGBT) for the electro- static discharge (ESD) protection of power ICs are presented. Compared with the conventional lateral DMOS with the same structure except for the anode doping type, the LIGBT shows lower triggering voltage, faster voltage-clamping speed, and much higher ESD robustness. Experimental results demonstrate that the LIGBT with runway layout achieves excellent thermal breakdown current of more than 10 A with 250-μm device width. The high ESD performance enables the LIGBT to be used as a promising ESD protection device in the power ICs.

A Novel Charge-Imbalance Termination for Trench Superjunction VDMOS

A novel charge-imbalance termination region for high-voltage trench superjunction (SJ) vertical diffused MOSFETs (SJ-VDMOSs) is proposed and discussed in this letter. Its breakdown characteristics are investigated theoretically and experimentally. A simple and meaningful analytical-solution method is proposed, and it agrees with the simulation and experimental results. As a result, the novel imbalance termination can suppress the edge-drift potential more effectively than the conventional one in the off state. When the trench SJ-VDMOS was compared with a conventional termination structure of the same size, the device improved the breakdown voltage (BV) by about 8% using the proposed termination structure. Experimentally, a BV of 715 V was obtained in the trench SJ-VDMOS with a 35-μm trench on a 45-μm epitaxial layer and a 90- μm termination region.

A novel latch-up free SCR-LDMOS for power-rail ESD clamp in half-bridge driver IC

The SCR-LDMOS device is a promising Electro Static Discharge (ESD) protection structure in high-voltage ICs for its high ESD robustness. However, its low holding voltage makes it susceptible to ESD-induced latch-up failure, especially used in the power-rail clamp circuits. This work presents a novel SCR-LDMOS with the NIL layer to achieve 17V holding voltage and 5.1A second breakdown current in a 0.5μm SOI process. The device has been applied for 15V power-rail ESD clamp in half-bridge driver IC.

Electrical Characteristic Investigation on a Novel Double-Well Isolation Structure in 600-V-Class High-Voltage Integrated Circuits

In order to achieve a high breakdown voltage (BV) and to avoid local breakdown in high-voltage integrated circuits, a novel double-well (DW) high-voltage divided reduced surface field (RESURF) isolation structure featuring two slender N-well regions located at N--well region is proposed for the first time. The breakdown mechanisms are investigated by theoretical analysis and experimental measurements. In the high-voltage blocking state, the N-well regions can efficiently prevent the P-well region from depleting with the high-side region, so as to maintain the charge balance of the novel isolation structure, which leads to an increase in the BV from 656 V in the conventional isolation structure to 760 V in the proposed structure. The dependence of the electrical characteristics of the isolation on the structure parameters has been analyzed in detail. The novel DW divided RESURF structure has been fabricated in 0.5- μm bipolar-CMOS-DMOS technology, which has verified the feasibility and validity of the new concept.

Investigation of the shift of hot spot in lateral diffused LDMOS under ESD conditions

This paper investigates the thermal behavior and thermal distribution of the high voltage LDMOS under Electrostatic Discharge (ESD) stress. It shows that the hot spots shift in both two-dimension and three-dimension during the snapback behavior and these spots are potential failure positions for the inferior structures. According to the different breakdown position, two improved adaptive structures which are verified by the simulations and experiment results are proposed. The article makes contribute to design more robust ESD protection power devices. The high voltage LDMOS is demonstrated in 0.5 μm CDMOS technology.

A novel double-well isolation structure for high voltage ICs

A novel double-well (DW) divided RESURF isolation structure featuring two slender N-Well regions at N--Well, aiming at improving the off-state breakdown voltage for high voltage IC (HVIC) is proposed in this paper. The N-Well regions in the presented structure efficiently prevent N--Well which used for the drift region of the Lateral Double Diffused MOSFET (LDMOS) from depleting with P-Well, so as to maintain the RESURF condition. The experiment results show that the proposed structure exhibits the breakdown voltage of 760V which has an improvement of 15% compared with the conventional structure.

Reliability Concern on Extended E-SOA of SOI Power Devices With P-Sink Structures

The P-sink structure is widely used in silicon-on-insulator (SOI) power devices (SOI-LIGBT and SOI-LDMOS) to extend the electrical safe operating area (E-SOA) as it can suppress the trigger of the parasitic transistor. In this paper, the electrical behavior and reliability issues in the extended E-SOA for 200-V SOI power devices with P-sink structures are investigated for the first time. For SOI-LIGBT, the normal I-V curve and small hot-carrier-induced degradation are observed in the extended E-SOA; thereby, the P-sink structure plays a good role. However, for SOI-LDMOS, two mechanisms dominate the electrical behavior in the extended E-SOA so as to bring the unusual “hump” in the I- V curve; meanwhile, it results in serious hot-carrier-induced degradation, reducing the lifetime of the device in practical applications. As a result, the P-sink structure is not the best choice to extend the E-SOA of SOI-LDMOS.

Novel Hot-Carrier Degradation Mechanisms in the Lateral Insulated-Gate Bipolar Transistor on SOI Substrate

The different hot-carrier degradation mechanisms of the lateral insulated-gate bipolar transistor on a silicon-on-insulator substrate (SOI-LIGBT) for different stress conditions have been experimentally investigated for the first time. For low Vgs and high Vds, the hot hole injects and traps into the accumulation and the field oxide, particularly the birds beak, which results in the decrease in the on-resistance Ron at the early stress stage. It is interesting that the decrease level of Ron in SOI-LIGBT is much more serious than that in the SOI laterally diffused metal-oxide-semiconductor with the same structure fully except for the doping type in the drain area. In addition, the buried oxide surface under the drain area also suffers from severe hot-carrier degradation. However, for high Vgs and low Vds, only hot-electron injection into the gate oxide near the source side can be observed; there is no hot-carrier degradation to be found in both the field and buried oxides.

An electrolytic capacitor‐less LED driver with interleaving flyback topology

Summary Here, we propose a single-stage alternating current/direct current electrolytic capacitor-less light-emitting diode (LED) driver, which applies interleaving flyback topology to reduce the peak-to-average ratio of LED driving current. With this approach, the peak current through LEDs is reduced, so the lifetime requirement of LEDs can be satisfied for an electrolytic capacitor-less LED driver. A new transformer with two interleaving auxiliary windings is applied to this driver. Based on this approach, compared with other electrolytic capacitor-less LED drivers, an important advantage of this driver is that it can be easily created, without additional control circuits. We will explain the operation principle and control strategy of the proposed driver in detail and will use experimental results taken from a 24-V 350-mA prototype to demonstrate its performance. Copyright