Longyan Wang

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The effect of O2 flow rate during the sputtered deposition of channel layer on the negative gate-bias stress (NGBS)-induced threshold voltage (Vth) instability of a-IGZO TFTs is investigated. It is shown that the negative gate-bias stress results in a negative Vth shift of the a-IGZO TFTs, and the shift amount decreases with the increase in O2 flow rate. It is proposed that the Vth shift originates from the electron-detrapping from the oxygen vacancy-related donor-like states at the channel/dielectric interface. As the O2 flow rate increases, the density of donor-like states is decreased and the distribution of neutral donor-like states below EF is also reduced. Therefore, the amount of Vth shift caused by the positively charged trap states and electrons injecting into the channel from the donor-like states decreases with the O2 flow rate increase. It is also shown experimentally that while the electrical characteristics of the a-IGZO TFTs are generally improved with the O2 flow rate increase, they are degraded if an excess O2 is introduced. An optimal O2/Ar flow rate ratio of about 5 sccm/45 sccm is suggested to make a trade-off between the electrical performances and the gate-bias stress-induced Vth instability.

{\rm O}_{2}

We have fabricated fully transparent Al-doped ZnO thin-film transistors (AZO TFTs) on a flexible plastic substrate at room temperature. A double-stacked channel structure composed of a high-density layer and a low-density layer is also investigated to improve the device performance. As-fabricated TFTs exhibit excellent electrical performance as well as optical performance, with a saturation mobility of 31.4 cm2 V-1 s-1, a drain current on/off ratio of about 108, a subthreshold swing of 330 mV/dec, and an average transmittance in the visible wavelength range of above 70%.

Flow Rate During Channel Layer Deposition on Negative Gate Bias Stress-Induced

A simple method of fabricating fully self-aligned double-gate (SADG) homojunction a-IGZO TFTs is proposed and experimentally demonstrated for the first time. The self-alignment between the bottom- and top-gates is realized with one backside-illuminated photolithographic step; and that between the source/drain regions and the two gates is formed by both argon plasma treatment and hydrogen doping. The resulting overlap between the gate and source/drain regions is about 0.3 μm. Excellent symmetry between bidirectional transfer characteristics in the fabricated SADG TFTs is observed. Moreover, the dynamic threshold voltage operation is well demonstrated, and the driving capability, electrical stress effects under tied and separate gate biases are investigated.

V_{\rm th}

We report low-temperature magnetotransport studies of individual InAs nanowires grown by molecule beam epitaxy. At low magnetic fields, the magnetoconductance characteristics exhibit a crossover between weak antilocalization and weak localization by changing either the gate voltage or the temperature. The observed crossover behavior can be well described in terms of relative scales of the transport characteristic lengths extracted based on the quasi-one-dimensional theory of weak localization in the presence of spin-orbit interaction. The spin relaxation length extracted from the magnetoconductance data is found to be in the range of 80–100 nm, indicating the presence of strong spin-orbit coupling in the InAs nanowires. Moreover, the amplitude of universal conductance fluctuations in the nanowires is found to be suppressed at low temperatures due to the presence of strong spin-orbit scattering.

Shift of a-IGZO TFTs

A new two-transistor pixel circuit in a current-biased voltage programming mode for active matrix-organic light emitting diode displays is proposed. The proposed circuit features a fixed current source and a conventional data line. The former offers a moderate bias current to compensate for the device performance variation or degeneration, and the latter provides pixels with voltage signals. It is demonstrated that both accurate and fast compensations can be realized in the proposed pixel circuit.

Fully Transparent Al-Doped ZnO Thin-Film Transistors on Flexible Plastic Substrates

In this paper, a four a-IGZO TFTs based pixel circuit with simultaneous VT compensation function for AMOLED is proposed. The proposed circuit can not only simplify the peripheral circuits of the panel, but also compensate for both positive and negative VT shift with a charging VT-generation method. Simulation results show that the current changes only by 18.9% and 3.9% when ΔVT is -3 V and 2 V, respectively. Furthermore, by applying the grouping driving scheme, the OLED lighting time can be largely increased which manifests superiority when applied to high resolution or high frame rate displays.

Implementation of Fully Self-Aligned Homojunction Double-Gate a-IGZO TFTs

A current-biased voltage-programmed (CBVP) pixel circuit for active-matrix organic light-emitting diode (AMOLED) displays is proposed. The pixel circuit can not only ensure an accurate and fast compensation for the threshold voltage variation and degeneration of the driving TFT and the OLED, but also provide the OLED with a negative bias during the programming period. The negative bias prevents the OLED from a possible light emitting during the programming period and potentially suppresses the degradation of the OLED.

Phase-coherent transport and spin relaxation in InAs nanowires grown by molecule beam epitaxy

A hybrid thin film transistor (TFT) technology is proposed and demonstrated, which features a simultaneous fabrication of amorphous silicon (a-Si) TFTs with low off-current and polycrystalline silicon (poly-Si) TFTs with high carrier mobility on one substrate in one single process. For the a-Si TFT fabrication, the active film is the as-deposited LPCVD a-Si film, whereas, for the poly-Si TFT fabrication, the poly-Si active film is the locally crystallized LPCVD a-Si film. The localized crystallization is realized via using metal-induced lateral crystallization (MILC) method. This proposed technology is applicable to active-matrix organic light-emitting diode (AMOLED) pixel circuits where switching TFTs and driving TFTs are required to be with low off-current and high on-current, respectively.

Two-Transistor Current-Biased Voltage-Programmed AM-OLED Pixel

A new back-channel-etched process for the fabrication of amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) is demonstrated, in which a conductive Nb doped TiO2 (TNO) thin film is used to serve as protective layer for the a-IGZO active layer. It is shown that the TNO film provides the active layer with excellent protection even when the thickness is only 1 nm. With treatment by N2O plasma +200°C annealing, the conductive TNO can be converted into an insulator to serve as an in situ passivation layer. Besides, by the introduction of the TNO layer, the source–drain parasitic resistance of the BCE process fabricated TFTs is significantly reduced and the positive bias stress stability is improved as well.

An a-IGZO TFT pixel circuit for AMOLED with simultaneous V T compensation

We propose a new active matrix organic light-emitting diode (AMOLED) pixel circuit in which the compensation for the thin film transistor and OLED performance variation and/or degeneration is performed periodically in a separate frame time. In the other frame time, the AMOLED pixel works without any compensation operation, so that the whole row time is used for driving. Only three transistors and two capacitors are required to construct the pixel circuit. It is demonstrated that both accurate compensation and high driving speed can be realized in the separate frame compensated AMOLED pixel circuit.