Lorenza Ferrario

SILICON PIN RADIATION DETECTORS WITH ON-CHIP FRONT-END JUNCTION FIELD EFFECT TRANSISTORS

Abstract We report on the latest results obtained from the development of a fabrication technology for PIN radiation detectors with on-chip front-end junction field effect transistors (JFETs) integrated on high-resistivity, FZ silicon. P-doped polysilicon back-side gettering prevented carrier lifetime degradation in spite of the relatively high thermal budget characterizing the fabrication process, allowing very low leakage currents ( ≃1 nA/cm 2 at full depletion) to be obtained. Results from JFETs electrical characterization are presented, showing high transconductance and output resistance values as well as low gate currents and input capacitance. JFETs performance is not affected by the high reverse-bias voltage required for detector operation, making these devices suitable for the fabrication of monolithical preamplifiers integrated on the detector chip.

Feasibility study for double-sided silicon microstrip detector fabrication at IRST

Abstract This paper is concerned with the preliminary results of a technological study aimed at the development of a fabrication process for double-sided AC-coupled silicon microstrip detectors. The approach adopted for the fabrication of both single-sided and double-sided detectors is presented, and the results from electrical tests performed on detectors and test structures are reported and discussed. Good electrical characteristics as well as an acceptable number of process-related defects have been obtained for these prototype detectors, thus demonstrating the feasibility of fabricating such devices at the IRST facility.

Design and optimization of an npn silicon bipolar phototransistor for optical position encoders

Abstract We describe an activity aimed at developing npn silicon bipolar phototransistors to be used in optical position encoders. Extensive numerical proces and device simulations have been carried out, providing the guidelines for the definition of the phototransistor fabrication process. Results from the electrical and optical characterization of manifactured devices are shown. With respect to the designed fabrication process, only a little adjustment of the technological parameters has been to be necessary to achieve a final product suitable for the intended application.

Optimization of TMAH etching for MEMS

Tetra-methyl ammonium hydroxide (TMAH) is an anisotropic silicon etchant that is gaining considerable use in silicon sensor micromachining due to its excellent compatibility with CMOS processing, selectivity, anisotropy and relatively low toxicity, as compared to the more used KOH and EDP etchants. In this paper, the influence of temperature and concentration of the TMAH solution together with oxidizer additions is studied in order to optimize the anisotropic silicon etching for MEMS fabrication. In particular this optimized etchant formulation has been employed at ITC-Irst in the development of a basic fabrication process for piezoresistive pressure sensors based on a silicon membrane and four resistors connected in a Weatherstone bridge configuration. The active element of the sensor, i.e. the thin silicon membrane, is formed by etching anisotropically from the backside of the wafer. Both process and etching have to be tuned and matched in order to obtain an optimum fabrication sequence. Some improvements such as higher etch rate and better surface finish have been obtained by the addition of ammonium peroxidsulfate as oxidizing agent under different conditions. This simplifies both the post processing and the tech set-up. The process parameters and the thermo-electro-mechanical characteristics of the pressure sensors were tested and are compared with the analytical and numerical simulations.

Development of a detector-compatible JFET technology on high-resistivity silicon

Abstract We report on the development of a radiation-detector compatible JFET technology on high-resistivity silicon for monolithic integration of detectors and front-end electronics. A dedicated test-chip has been designed and fabricated for process and device characterization. Results from the electrical characterization of a first fabrication run show that good values of detector leakage current ( ≈1 nA/cm 2 ) can be obtained in spite of the relatively high thermal budget characterizing the process. As far as the JFET performance is concerned, a problem of insufficient device isolation at high substrate voltages has been evidenced. A second run is currently being carried on with the aim of optimizing the JFET structure.

Development of silicon microheaters for chemoresistive gas sensors

We report on the design, fabrication, and characterization of a microheater module for chemoresistive, metal-oxide semiconductor gas sensors, consisting of a dielectric stacked membrane, micromachined from bulk silicon and with an embedded polysilicon resistor heater. Fabricated structures exhibit excellent heating efficiency, requiring only 30 mW to achieve a temperature of 500 C. Measured electrothermal characteristics are in good agreement with the outcomes of 3D numerical simulations.

AUTOMATIC ORDER REDUCTION FOR FINITE ELEMENT MODELS

In the process of physical modelling of microsystems operating on various energy domains, the engineer is used to apply Finite Element techniques for the discrete representation of the functionality of the device under investigation in a simulation environment. There are many commercial products that help the engineer in performing this task. The common feature of all these simulation tools is that the discrete representation consists of a system of ordinary differential equations. The dimension of this system is directly connected to the number of degrees of freedom for the respective problem. For a spatial displacement field, e.g., the degrees of freedom are three times the number of discretization nodes. The higher the requirements for precision of the simulation results, the more discretization nodes are usually introduced. Nevertheless, the results the engineer will use are in most cases of low dimensional order. In other words, the characteristic features of the required functionality of the device under developement are well represented in low dimensional subspace of the entire solution space of a very fine Finite Element model. Moreover, the requirement for system behaviour simulation makes it impossible to couple large-scale

Process stress estimation for MEMS RF switches with mixed analytical and numerical simulation

One of the basic parameters in RF capacitive switches is the actuation voltage. It strongly depends on the process stress accumulated in the switching structure, typically a suspended thin bridge, made of conductive materials. The control and the tuning of the deposition steps require the monitoring and the reduction of the process stress. We present a method to estimate the global process stress of the device taking advantage of the electrical characterization done on standard capacitive test structures integrated in the process layout.

A computerised analysis tool for the electrical characterisation of microstrip detectors

Abstract We report on a computer tool, based on Perl programming language, providing automatic analysis of experimental data from microstrip detector parametric measurements. Besides handling graphical display of data and statistical calculations, the program is intended to check for possible process-related problems by correlating the various measurements. The proposed software has proved itself to be a useful tool for the development of double-sided AC-coupled microstrip detectors at IRST, successfully identifying several process-related defects, as confirmed by optical inspection of the wafers.

An all-implanted p-channel Si JFET fully compatible with CMOS technology

Abstract In this article, we show that a p-channel silicon Junction Field Effect Transistors (JFET) can be obtained within a conventional CMOS n-well technology with no additional process steps but a simple layout modification of the p-channel-stop mask; in fact, in the suggested technology, the p-channel of the JFET is obtained by using the same CMOS p-stop implantation step. Results from the electrical characterization of a specially designed test-chip confirmed the validity of the device concept and its full compatibility with CMOS devices; in particular, JFETs exhibit high transconductance and output resistance as well as low gate current and input capacitance. The proposed technological approach has therefore proved to be suitable for the realization of p-JFET–CMOS low-noise circuits.