G.-F. Dalla Betta

Electrical Characterization of Silicon Photo-Multiplier Detectors for Optimal Front-End Design

Silicon Photo-Multiplier (SiPM) detectors represent an attractive solution for the detection of low energy photons in several fields of both high energy physics and medical imaging. We present here an accurate electrical model for this kind of detectors, which can be conveniently used to perform reliable simulations at circuit level. A suitable extraction procedure for the parameters involved in the model is also described, based on both static and dynamic measurements. The proposed model allows to reproduce accurately the waveform of the signal generated by the SiPM when coupled to the front-end electronics, as shown by excellent fittings obtained between simulations and measurements taken on real devices. This is particularly useful in order to choose the most suitable front-end architecture for SiPM detectors, since the performance of the whole detection system, especially in terms of dynamic range and timing resolution, can be correctly predicted as a function of the detector parameters and of the main characteristics of the coupled electronics.

Slim edges in double-sided silicon 3D detectors

Minimization of the insensitive edge area is one of the key requirements for silicon radiation detectors to be used in future silicon trackers. In 3D detectors this goal can be achieved with the active edge, at the expense of a high fabrication process complexity. In the framework of the ATLAS 3D sensor collaboration, we produced modified 3D silicon sensors with a double-sided technology. While this approach is not suitable to obtain active edges, because it does not use a support wafer, it allows for a new type of edge termination, the slim edge. In this paper we report on the development of the slim edge, from numerical simulations to design and testing, proving that it works effectively without increasing the fabrication complexity of silicon 3D detectors, and that it could be further optimized to reduce the insensitive edge region to less than 100 μm.

Study of breakdown effects in silicon multi-guard structures

Many applications of silicon p/sup +/-n junctions as detectors require high voltage operation. In particular the LHC experiments, because of the radiation damage level, need very high bias working voltage to fully collect the ionising generated charge multi-guard structures can be used in order to improve the breakdown voltage of microstrip detectors, limiting the occurrence of critical fields in the proximities of a reverse biased p/sup +/-n junction. In this work we present results for different designs of multi-guard structures, before and after irradiation with ionising and non-ionising radiation sources (p,n,/spl gamma/), and for different doses. Various experimental techniques have been used, like DC and AC electrical characterizations, and light emission microscopy. Moreover, a simulation work is presented. Its purpose is to improve the design on the basis of the experimental results.

Recent developments on silicon photomultipliers produced at FBK-irst

In this contribution, new developments on the silicon photomultipliers (SiPMs) fabricated at FBK-irst (Trento, Italy) are reported. With respect to the first series of devices produced in 2005/2006, there have been major improvements on both the the layout and the technology. Concerning the first aspect we fabricated SiPMs with increased fill factor and with different geometries (square/circular devices, arrays and matrices of SiPMs) to meet the requirements of different applications. Concerning the technology, we identified a process technique able to reduce significantly the dark count rate. In this paper we will describe the main electro-optical characteristics of these devices.

Novel Silicon Photomultipliers for PET Applications

Silicon photomultipliers (SiPMs) with quantum efficiency maximized for a wavelength between 420 and 470 nm have been developed at ITC-irst Trento (Italy), and are being tested for their application in the construction of a ultra high resolution small animal PET tomograph. The devices have an area of 1 mm times 1 mm and 625 microcells. The breakdown voltage is around 30 V, and the gain of the order of 106. The intrinsic timing resolution is 70 ps rms at the single photoelectron level. The first tests as readout for scintillators show an energy resolution of 21% FWHM with Na-22 employing LSO crystals. The first matrices of SiPMs have been produced and are being tested.

Development of a fabrication technology for double-sided AC-coupled silicon microstrip detectors

Abstract We report on the development of a fabrication technology for double-sided, AC-coupled silicon microstrip detectors for tracking applications. Two batches of detectors with good electrical figures and a low defect rate were successfully manufactured at IRST Laboratory. The processing techniques and the experimental results obtained from these detector prototypes are presented and discussed.

Development of deep N-well MAPS in a 130 nm CMOS technology and beam test results on a 4k-pixel matrix with digital sparsified readout

We report on further developments of our recently proposed design approach for a full in-pixel signal processing chain of deep n-well (DNW) MAPS sensors, by exploiting the triple well option of a CMOS 0.13 μm process. The optimization of the collecting electrode geometry and the re-design of the analog circuit to decrease power consumption have been implemented in two versions of the APSEL chip series, namely “APSEL3T1” and “APSEL3T2”. The results of the characterization of 3x3 pixel matrices with full analog output with photons from 55Fe and electrons from 90Sr are described. Pixel equivalent noise charge (ENC) of 46 e- and 36 e- have been measured for the two versions of the front-end implemented toghether with signal-to-noise ratios between 20 and 30 for Minimum Ionizing Particles. In order to fully exploit the readout capabilities of our MAPS, a dedicated fast readout architecture performing on-chip data sparsification and providing the timing information for the hits has been implemented in the prototype chip “APSEL4D”, having 4096 pixels. The criteria followed in the design of the readout architecture are reviewed. The implemented readout architecture is data-driven and scalable to chips larger than the current one, which has 32 rows and 128 columns. Tests concerning the functional characterization of the chip and response to radioactive sources have shown encouraging preliminary results. A successful beam test took place in September 2008. Preliminary measurements of the APSEL4D charge collection efficiency and resolution confirmed the DNW device is working well. Moreover the data driven approach of the readout chips has been successfully used to demonstrate the possibility to build a Level 1 trigger system based on Associative Memories.

Si-PIN X-ray detector technology

Abstract PIN diodes and other test structures have been fabricated on both n- and p-type, high-resistivity, Floating-Zone (FZ) silicon substrates. Different alternative extrinsic-gettering techniques have been adopted to the purpose of meeting the required specification of a detector leakage current density lower than 1 nA/cm2. Phosphorus-doped polysilicon gettering provided the best results on n-type Si with a leakage current density lower than 0.2 nA/cm2 at 100 μm depletion width. On the contrary, devices made on p-type substrates exhibited a leakage current density two orders of magnitude higher. A proper control of the oxide charge at the silicon-silicon dioxide interface was found to be crucial in obtaining a predictable behavior of PIN diode detectors. Some degradation of the reverse leakage current has been observed after device dicing and bonding.

Test beam results of 3D silicon pixel sensors for the ATLAS upgrade

Results on beam tests of 3D silicon pixel sensors aimed at the ATLAS Insertable B-Layer and High Luminosity LHC (HL-LHC) upgrades are presented. Measurements include charge collection, tracking efficiency and charge sharing between pixel cells, as a function of track incident angle, and were performed with and without a 1.6 T magnetic field oriented as the ATLAS inner detector solenoid field. Sensors were bump-bonded to the front-end chip currently used in the ATLAS pixel detector. Full 3D sensors, with electrodes penetrating through the entire wafer thickness and active edge, and double-sided 3D sensors with partially overlapping bias and read-out electrodes were tested and showed comparable performance.

Preliminary results from a current mode CMOS front-end circuit for silicon photomultiplier detectors

We propose a CMOS front-end circuit suitable for Silicon Photomultiplier detectors (SiPM) based on a current buffer, as input stage, which features small input impedance and large bandwidth, thanks to the application of current feedback techniques. The current mode approach enhances the dynamic range of the front-end and does not suffer from possible voltage limitations due to deep-submicron CMOS implementation. We report the first measurement results obtained by coupling the circuit prototype to a SiPM detector excited by a blue LED light source. The measurements confirm the effectiveness of the proposed front-end approach and demonstrate its capability of managing large current signals with good linearity.