Lorenzo Cerati

CDM circuit simulation of a HV operational amplifier realized in 0.35um smart power technology

CDM circuit simulations feasibility on complex smart power circuits is presented in this work and applied to a high voltage operational amplifier. Simulation results are validated by means of measurements on dedicated test circuits and failure analysis. Pre-requisites for simulations and device model improvements are deeply investigated by means of vf-TLP measurements.

Development of ESD protection structures for BULK and SOI BCD6 technology

ESD protection elements for 0.35mum smart power technology on SOI substrate are investigated, considering bulk technology as a reference. Heat dissipation issue, due to oxide isolation, is analyzed at simulation level. Starting from simulation results, proper sizing and ESD robustness verification are presented

Schematic-Level and Layout-Level ESD EDA check methodology applied to smart power IC's - initialization and implementation

A functional methodology to fully check IC ESD network topology together with protected circuitry ESD compliance at Schematic-Level and metal interconnections at Layout-Level is developed and applied to Smart Power products. A common operational method is developed to simultaneously initialize different Schematic-Level and Layout-Level verification tools.

EDA checker for identification of excessive ESD voltage drop-implementation to smart power IC's

A customized checker able to calculate HBM voltage drop and to identify product circuitry prone to excessive over voltages is ideated, implemented, and successfully applied to Smart Power products. This checker is conceived as part of a complete verification flow covering all main aspects of IC designs ESD compliance.

HV ESD diodes investigation under vf-TLP stresses: TCAD approach

Very fast TLP stresses applied to HV ESD diodes in forward conduction are able to reproduce well known and CDM typical effects as Forward Recovery. In this work a full RLC vf-TLP model is introduced in order to investigate HV ESD diodes electrical and physical behavior using TCAD mixed-mode simulations.

Thin-Copper-Metal Interconnection Thermomigration Analysis in ESD Regime

The technological scaling is posing severe constraints on metal interconnections design, especially for ESD protection network routing in advanced Smart-power technologies. A detailed analysis of thin interconnections failure mechanisms under high power pulses and of the related root causes is mandatory. In this paper this analysis is illustrated by use of characterizations, failure analyses and 3D TCAD physical simulations data.

Breakdown characterization of gate oxides in 35 and 70 Å BCD8 smart power technology.

The breakdown of 35 A and 70 A thick NMOS and PMOS silicon Gate oxides used in 1.8 V and 3.3 V BCD8 Smart Power technological node was investigated in this work. Both voltage to breakdown, from DC down to the ESD time domain, and time-dependent breakdown analysis have been carried out. We present also the evidence that breakdown is not affected by cumulative stress and it is mainly driven by voltage stress.