Lucia Zullino

Characterization and modeling of transient device behavior under CDM ESD stress

Device physical effects that strongly influence the transient behavior during very fast, high current pulses are discussed. The effects are studied by experimental characterization and device simulation. The dependence on the technology (deep-sub-micron, smart-power/high-voltage) is considered as well. Compact models for CDM circuit simulation are developed.

20V-40V Symmetrical Vertical Trench nMOS (SVT MOS) design for display driver ICs

This paper presents a novel 20V/40V symmetrical vertical trench MOS (SVT MOS) having both drain extension and gate realized in vertical direction respect to the silicon surface. Using silicon depth to realize the gate and to withstand high voltage, carefully designing doping implants and realizing a vertical field oxide, it was possible to reduce more than 60% the device pitch (i.e. spacing between half drain contact and half source contact) maintaining the same performance of equivalent lateral device

Internal behavior of BCD ESD protection devices under TLP and very-fast TLP stress

BCD electrostatic discharge (ESD) protection npn devices with different layout variations are analyzed experimentally and by device simulation. The device internal thermal and free carrier density distributions during the transmission line pulse (TLP) and very-fast transmission line pulse (vf-TLP) stresses are studied by a backside transient interferometric mapping technique. The lateral part of the npn transistor dominates the devices operation. The action of the vertical part of the transistor is influenced by the device layout. Experimentally observed activity of both parts of the npn transistor is well reproduced by the simulation. The devices exhibit an excellent ESD performance at both TLP and vf-TLP stress.

HV ESD diodes investigation under vf-TLP stresses: TCAD approach

Very fast TLP stresses applied to HV ESD diodes in forward conduction are able to reproduce well known and CDM typical effects as Forward Recovery. In this work a full RLC vf-TLP model is introduced in order to investigate HV ESD diodes electrical and physical behavior using TCAD mixed-mode simulations.

H 2 annealing for metallic contaminant reduction in BCD-SOI process: Benefits and drawbacks

Contaminant reduction is a key issue for SOI substrate which cannot make use of back-side gettering. H2 annealing has been proven to be effective in Si reconstruction, influencing diffusion by breaking strained Si bonds and generating cavities for contaminant gettering. These properties could help in reducing contaminants in BCD-SOI process. Unfortunately, H2 annealing integration can be highly critical and the process optimization has to take into account 3-D morphology evolution and contaminant reduction efficiency. Aim of this work is to understand the physical mechanisms behind Si surface reconstruction and metallic contaminants reduction.

Thin-Copper-Metal Interconnection Thermomigration Analysis in ESD Regime

The technological scaling is posing severe constraints on metal interconnections design, especially for ESD protection network routing in advanced Smart-power technologies. A detailed analysis of thin interconnections failure mechanisms under high power pulses and of the related root causes is mandatory. In this paper this analysis is illustrated by use of characterizations, failure analyses and 3D TCAD physical simulations data.